Enhancing delay fault coverage through low-power segmented scan

Zhang, Z.; Reddy, S.M.; Pomeranz, Irith; Rajski, J.; Al-Hashimi, B.M.

doi:10.1049/iet-cdt:20060135

Cited by 10 publications

(22 citation statements)

References 16 publications

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“…In Table III, our method is compared with the methods in [9] and [18] with respect to peak capture power, average capture power, test-data volume and test application time. The methods in [9] and [18] can reduce capture power for broadside testing, but they increase the test-data volume and test application time considerably.…”

Section: Comparison With Other Methodsmentioning

confidence: 99%

“…The methods in [9] and [18] can reduce capture power for broadside testing, but they increase the test-data volume and test application time considerably. We implemented the methods presented in [9] and [18] to compare than with the proposed technique.…”

Section: Comparison With Other Methodsmentioning

confidence: 99%

“…However, many DFT-based methods are applicable only to stuck-at fault testing [10,14] and they cannot be used to reduce capture power in the launch cycle or capture cycle for broadside testing. Methods that reduce capture power for broadside testing suffer from the drawback of increased testdata volume [9,18], or significant hardware overhead [8]. A new approach is therefore needed to reduce capture power for broadside testing, with minimum impact on test-data volume and hardware overhead.…”

Section: Introductionmentioning

confidence: 99%

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MVP: Capture-power reduction with minimum-violations partitioning for delay testing

Chen¹,

Chakrabarty²,

Xiang³

2010

2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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Abstract-Scan shift power can be reduced by activating only a subset of scan cells in each shift cycle. In contrast to shift power reduction, the use of only a subset of scan cells to capture responses in a cycle may cause capture violations, thereby leading to fault coverage loss. In order to restore the original fault coverage, new test patterns must be generated, leading to higher test-data volume. In this paper, we propose minimum-violations partitioning (MVP), a scan-cell clustering method that can support multiple capture cycles in delay testing without increasing test-data volume. This method is based on an integer linear programming model and it can cluster the scan flip-flops into balanced parts with minimum capture violations. Based on this approach, hierarchical partitioning is proposed to make the partitioning method routingaware. Experimental results on ISCAS'89 and IWLS'05 benchmark circuits demonstrate the effectiveness of our method.

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Section: Comparison With Other Methodsmentioning

confidence: 99%

Section: Comparison With Other Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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MVP: Capture-power reduction with minimum-violations partitioning for delay testing

Chen¹,

Chakrabarty²,

Xiang³

2010

2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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“…Segmented scan is one of the techniques for improving the fault coverage [26]. Consider the part of a sequential circuit shown in Fig.…”

Section: Segmented Scanmentioning

confidence: 99%

Improving Small-Delay Fault Coverage of On-Chip Delay Measurement by Segmented Scan and Test Point Insertion

Zhang

Namba

Ito

2014

IEICE Trans. Inf. & Syst.

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SUMMARYWith IC design entering the nanometer scale integration, the reliability of VLSI has declined due to small-delay defects, which are hard to detect by traditional delay fault testing. To detect small-delay defects, on-chip delay measurement, which measures the delay time of paths in the circuit under test (CUT), was proposed. However, our pre-simulation results show that when using on-chip delay measurement method to detect small-delay defects, test generation under the single-path sensitization is required. This constraint makes the fault coverage very low. To improve fault coverage, this paper introduces techniques which use segmented scan and test point insertion (TPI). Evaluation results indicate that we can get an acceptable fault coverage, by combining these techniques for launch off shift (LOS) testing under the single-path sensitization condition. Specifically, fault coverage is improved 27.02∼47.74% with 6.33∼12.35% of hardware overhead.

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“…These techniques rely on test-pattern ordering [29]- [32], scan chain ordering [23], [33], [34], and the use of multiple capture cycles during test application [29] to reduce the toggling of scan cells during shift/capture cycles. Segmented scan approaches [20], [21], [35] have also been used to address test power issues for industrial designs.…”

Section: A Backgroundmentioning

confidence: 99%

Power Management Using Test-Pattern Ordering for Wafer-Level Test During Burn-In

Bahukudumbi

Chakrabarty

2009

IEEE Trans. VLSI Syst.

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Abstract-Wafer-level test during burn-in (WLTBI) is a promising technique to reduce test and burn-in costs in semiconductor manufacturing. However, scan-based testing leads to significant power variations in a die during test-pattern application. This variation adversely affects the accuracy of predictions of junction temperatures and the time required for burn-in. We present a test-pattern ordering technique for WLTBI, where the objective is to minimize the variation in power consumption during test application. The test-pattern ordering problem for WLTBI is formulated and solved optimally using integer linear programming. Efficient heuristic methods are also presented to easily solve the pattern-ordering problem for large circuits. Simulation results are presented for the ISCAS'89 and the IWLS'05 benchmark circuits, and the proposed ordering technique is compared with two baseline methods that carry out pattern ordering to minimize peak power and average power, respectively. A third baseline method that randomly orders test patterns is also used to evaluate the proposed methods. Index Terms-Wafer-level test during burn-in (WLTBI), test-pattern ordering, test power.

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Enhancing delay fault coverage through low-power segmented scan

Cited by 10 publications

References 16 publications

MVP: Capture-power reduction with minimum-violations partitioning for delay testing

MVP: Capture-power reduction with minimum-violations partitioning for delay testing

Improving Small-Delay Fault Coverage of On-Chip Delay Measurement by Segmented Scan and Test Point Insertion

Power Management Using Test-Pattern Ordering for Wafer-Level Test During Burn-In

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