Enhancing NBTI Recovery in SRAM Arrays Through Recovery Boosting

Siddiqua, Taniya; Gurumurthi, Sudhanva

doi:10.1109/tvlsi.2011.2109973

Cited by 29 publications

(19 citation statements)

References 18 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In our simulation, the temperature is 90°C, which is the average operating temperature for high-performance processors [21]. As expected, because of the asymmetrical structure of RF bit-cells, the power characteristics are data dependent.…”

Section: E Circuit-level Evaluations On Power Efficiencymentioning

confidence: 70%

“…In [20], an adaptive body bias technique was introduced to reduce the impact of NBTI and process variation. Most recently, Siddiqua and Gurumurthi [21] proposed recovery boosting RF which allows both pMOS devices in the bit-cell to be put into the recovery mode. In [22], a hybrid-cell RF design was presented to mitigate NBTI-induced degradation by storing more vulnerable data bits in the robust 8T cells and the less vulnerable bits in the conventional 6T cells.…”

Section: B Related Work On Reliable Rf Designmentioning

confidence: 99%

See 1 more Smart Citation

TM-RF: Aging-Aware Power-Efficient Register File Design for Modern Microprocessors

Gong

Wang

Jiang

et al. 2015

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

Modern microprocessors employ register files (RFs) for performance enhancement and achieving instruction level parallelism simultaneously. However, RF incurs large power consumption owing to the highly frequent access. Meanwhile, as technology scales, bias temperature instability has become a major reliability concern for RF designers. This paper presents an aging-aware trimodal register file (TM-RF) design to enhance the power efficiency. As instructions pass through the pipeline, TM-RF places the bit-cells in different modes based on the register activity, thereby achieving significant power reduction. To meet design constraints of different applications, we present four schemes to implement the proposed design, providing design flexibility. Additionally, with device selection and worst case sizing methodology, we mitigate aging-effect-induced RF reliability degradation. Simulation results on SPEC 2000 benchmarks demonstrate that TM-RF achieves up to 81.4% power savings and 17% reliability improvement on average, with minimal impact on performance.Index Terms-Leakage current, low power, bias temperature instability (NBTI/PBTI), process variation, register file (RF). 1063-8210

show abstract

Section: E Circuit-level Evaluations On Power Efficiencymentioning

confidence: 70%

Section: B Related Work On Reliable Rf Designmentioning

confidence: 99%

TM-RF: Aging-Aware Power-Efficient Register File Design for Modern Microprocessors

Gong

Wang

Jiang

et al. 2015

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

show abstract

“…As such, it does not relieve any HCI aging compared to our other schemes but can be beneficial as equally aged transistors have smaller leakage power. The DCM mode can also be coupled with NBTI recovery schemes such as [21]. We explain the DCM mode in more detail in Section S4.…”

Section: Distributed Cycle Mode (Dcm)mentioning

confidence: 99%

“…While there has been a wide scope of studies tackling different reliability issues (NBTI, TDDB, HCI) in processing elements [11,21], there is only a limited number of works which address wear-out mitigation in the on-chip communication infrastructure of such systems. Bhardwaj et al implemented a dynamic routing algorithm to equalize NBTI and electromigration aging across the on-chip network [3].…”

Section: Related Workmentioning

confidence: 99%

HCI-tolerant NoC router microarchitecture

Ancajas

Nickerson

Chakraborty

et al. 2013

Proceedings of the 50th Annual Design Automation Conference

View full text Add to dashboard Cite

The trend towards massive parallel computing has necessitated the need for an On-Chip communication framework that can scale well with the increasing number of cores. At the same time, technology scaling has made transistors susceptible to a multitude of reliability issues (NBTI, HCI, TDDB). In this work, we propose an HCI-Tolerant microarchitecture for an NoC Router by manipulating the switching activity around the circuit. We find that most of the switching activity (the primary cause of HCI degradation) are only concentrated in a few parts of the circuit, severely degrading some portions more than others. Our techniques increase the lifetime of an NoC router by balancing this switching activity. Compared to an NoC without any reliability techniques, our best schemes improve the switching activity distribution, clock cycle degradation, system performance and energy delay product per flit by 19%, 26%, 11% and 17%, respectively, on an average.

show abstract

“…This chapter covers work published in ISVLSI 2010 [2] and in the IEEE Transactions on VLSI 2011 [3].…”

Section: Discussionmentioning

confidence: 99%

A Multi-Level Approach to NBTI Mitigation in Processors

Siddiqua

Self Cite

View full text Add to dashboard Cite

We are in the era of multicore processors and it is expected that the number of the processing cores on a chip will steadily increase over the next decade, driven by Moore's Law. While technology scaling has benefitted high performance, the scaling has a dark side too: a degradation in the reliability of silicon devices. Processors have become highly susceptible to a variety of reliability problems in silicon, such as particle induced soft errors and hard errors. Therefore, processors have to be designed to provide adequate protection against these reliability problems while maintaining high performance and energy efficiency. Designing a reliable computer system is a large and complex multi-dimensional and multi-level problem, comprising of different hardware blocks, reliability phenomena, design layers, metrics, and optimization techniques. This dissertation considers a key emerging reliability phenomenon: Negative Bias Temperature Instability (NBTI). This dissertation develops NBTI mitigation techniques for the logic and memory structures in the processor that impose very little performance, power, and area overheads. This research also creates the foundation for understanding NBTI in the context of one other important processor reliability problem: process variations.

show abstract

Enhancing NBTI Recovery in SRAM Arrays Through Recovery Boosting

Cited by 29 publications

References 18 publications

TM-RF: Aging-Aware Power-Efficient Register File Design for Modern Microprocessors

TM-RF: Aging-Aware Power-Efficient Register File Design for Modern Microprocessors

HCI-tolerant NoC router microarchitecture

A Multi-Level Approach to NBTI Mitigation in Processors

Contact Info

Product

Resources

About