Enhancing performance of Tall-Skinny QR factorization using FPGAs

Abstract

Communication-avoiding linear algebra algorithms with low communication latency and high memory bandwidth requirements like Tall-Skinny QR factorization (TSQR) are highly appropriate for acceleration using FPGAs. TSQR parallelizes QR factorization of tall-skinny matrices in a divideand-conquer fashion by decomposing them into sub-matrices, performing local QR factorizations and then merging the intermediate results. As TSQR is a dense linear algebra problem, one would therefore imagine GPU to show better performance. However, the performance of GPU is limited by the memory bandwidth in local QR factorizations and global communication latency in the merge stage. We exploit the shape of the matrix and propose an FPGA-based custom architecture which avoids these bottlenecks by using high-bandwidth on-chip memories for local QR factorizations and by performing the merge stage entirely on-chip to reduce communication latency. We achieve a peak doubleprecision floating-point performance of 129 GFLOPs on Virtex-6 SX475T. A quantitative comparison of our proposed design with recent QR factorization on FPGAs and GPU shows up to 7.7× and 12.7× speed up respectively. Additionally, we show even higher performance over optimized linear algebra libraries like Intel MKL for multi-cores, CULA for GPUs and MAGMA for hybrid systems.

Population-Based MCMC on Multi-Core CPUs, GPUs and FPGAs

“…If data is kept inside the device or a data reuse scheme can be devised (e.g. [33]), this benefits the FPGA.…”

“…This can be a disadvantage for memory-bound likelihood computations. Nevertheless, FPGAs enjoy massive on-chip memory bandwidth (20-40 TB/sec [33]) due to large amounts of built-in memory. GPU on-chip memory bandwidths are limited to 8 TB/sec and 1.5 TB/sec [33].…”

“…Nevertheless, FPGAs enjoy massive on-chip memory bandwidth (20-40 TB/sec [33]) due to large amounts of built-in memory. GPU on-chip memory bandwidths are limited to 8 TB/sec and 1.5 TB/sec [33]. If data is kept inside the device or a data reuse scheme can be devised (e.g.…”

Joint Frequency and Time Estimation Algorithms

“…The least squares method (LS) or total least squares (TLS) [14] can be applied to find the frequencies of multiple incident sources. The proposed methods employ the LU factorization and the TLS to estimate the unknown frequency ω i similar to the ESPRIT algorithm using the following steps:…”

Using reconfigurable computing technology to accelerate matrix decomposition and applications

“…Previous FPGA-based implementations have looked at SVD [Brent and Luk (1982)], QRD [Wang and Leeser (2009)] and sparse LUD [Kapre and DeHon (2009)]. However, those approaches all have some limitations in common: either restricted with the scalability of the adapted matrices due to the logic capacity of FPGAs [Brent and Luk (1982); Ahmedsaid et al (2003); Ma et al (2006); Ledesma-Carrillo et al (2011); Wang and Leeser (2009)] or required the input matrices of special property or irregular sparsity structure [Rafique et al (2012);Tai et al (2011); Vachranukunkiet (2007); Kapre and DeHon (2009); Wu et al (2012)].…”