2014
DOI: 10.14810/elelij.2014.3403
|View full text |Cite
|
Sign up to set email alerts
|

Enhancing Phase-Margin of OTA Using Self-Biasing Cascode Current Mirror

Abstract: In this paper, a new adaptive biased low voltage cascode current mirror with high input/output swing is presented. This advantage is achieved using a self-biasing transistor and compensation resistor. The new structure profits from better input dynamic range and lower supply voltage without frequency response limitation and increasing input impedance. Also, the proposed current mirror is incorporated in folded cascode amplifier in order to enhance its phase-margin. The simulation results in 0.18 µm CMOS techno… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2

Citation Types

0
2
0

Year Published

2015
2015
2019
2019

Publication Types

Select...
3

Relationship

0
3

Authors

Journals

citations
Cited by 3 publications
(2 citation statements)
references
References 8 publications
0
2
0
Order By: Relevance
“…In [9], an adaptive improved recycling folded cascode amplifier with improved gain, high slew rate, high phase margin, and reduced power consumption was discussed. In [10], a self bias cascode current mirror with frequency compensation is utilized for enhancing the phase margin of the RFC OTA. In [11], the FC OTA was * Correspondence: kumaravel.s@vit.ac.in implemented for achieving higher DC gain and unity gain bandwidth with low power consumption using the enhanced recycling technique by operating all the transistors in the subthreshold region.…”
Section: Introductionmentioning
confidence: 99%
“…In [9], an adaptive improved recycling folded cascode amplifier with improved gain, high slew rate, high phase margin, and reduced power consumption was discussed. In [10], a self bias cascode current mirror with frequency compensation is utilized for enhancing the phase margin of the RFC OTA. In [11], the FC OTA was * Correspondence: kumaravel.s@vit.ac.in implemented for achieving higher DC gain and unity gain bandwidth with low power consumption using the enhanced recycling technique by operating all the transistors in the subthreshold region.…”
Section: Introductionmentioning
confidence: 99%
“…This design follows three stages such as (i) Input Pair, (II) Current mirror Cascode Stage and (III) Biasing Stage. Current mirror is a one type of approach to copy current at output side [4].…”
Section: Introductionmentioning
confidence: 99%