By using the XOR method to obfuscate response of Arbiter PUFs (APUFs), the ability to resist machine learning (ML) modeling attacks can be improved, but this method will reduce the stable of PUF to a certain extent, making PUF lose usability. In view of this, a highly stable XOR APUF (HS-XOR APUF) circuit is proposed by studying the generation mechanism of unstable response bits and the screening characteristics of the logic gates delay signals. First, the maximum and minimum delay signals are screened with AND/OR gate to generate highly stable response bits; Then, by inserting a inverter in the APUF switch unit, the delay time of the signal is increased, and the influence of environmental factors on the comparison signal with small delay deviation is weakened; Finally, the FPGA experimental results show that the response stability of HS-XOR APUF is rarely affected by the count of XOR units, and the AND/OR gate delay signal screening structure is simple and consumes a small amount of hardware resources, which can be widely used in the fields of information security.