Electrochemical atomic layer deposition (e-ALD) process for fabricating cobalt (Co) nano-films is reported. The e-ALD process employs a two-step approach in which underpotential deposition (UPD) is first used to form a sacrificial adlayer of zinc (Zn) on a ruthenium (Ru) substrate. The sacrificial Zn adlayer then undergoes spontaneous surface-limited redox replacement (SLRR) by nobler Co. This provides an atomic layer of Co on the substrate surface. The two-step process is repeated cyclically to build multilayers of Co. The unique feature of the e-ALD approach presented herein is that it utilizes Zn as the sacrificial adlayer instead of Pb or Cu used conventionally in the e-ALD sequence of noble metals. The use of sacrificial Zn uniquely renders its redox replacement by Co to be thermodynamically favorable, thereby enabling Co e-ALD. In the present report, we discuss the electrochemical characteristics of the UPD and SLRR process steps, the e-ALD deposition rate and the deposit surface roughness. The Co deposits formed via e-ALD do not exhibit roughness amplification during the first 10 cycles of e-ALD, which is indicative of atomic-scale layer-by-layer growth of Co on the underlying Ru substrate. High-performance integrated circuits utilize nano-scale, currentcarrying copper (Cu) interconnects. In accordance with the Moore's law, 1 miniaturized interconnects are required in modern devices to obtain superior device performance. The continued shrinkage in the size (cross-sectional area) of each interconnect leads to an increase in its electrical resistance. This detrimentally impacts the electrical performance of the integrated circuit.2 Furthermore, aggressive interconnect size scaling below the 10 nm node poses challenges to void-free interconnect fabrication. State-of-the-art interconnects are fabricated of Cu metal due to its low electrical resistivity and superior electromigration resistance.3 The interconnect signal delay (τ) is given by τ = RC, where R is the interconnect resistance and C is the capacitance of the surrounding inter-layer dielectric. The interconnect resistance R increases dramatically for Cu interconnect dimensions below 40 nm due to the substantial increase in the electrical resistivity of Cu at such narrow dimensions. The resistivity increase is typically attributed to electron scattering processes at grain boundaries and at interfaces within the Cu interconnect structure. Such scattering processes become dominant when the interconnect dimension approaches the electron mean free path (EMFP = 39 nm at room temperature) in Cu.4,5 As a consequence, the interconnect signal delay increases. To overcome this critical issue, an interconnect material which exhibits lower electrical resistivity at narrow (sub 10 nm) dimensions is required. Cobalt (Co) is considered as a promising alternative interconnect material to replace the conventionally used Cu.6,7 At narrow dimensions, i.e., below 10 nm, Co exhibits comparable or lower electrical resistivity compared to Cu, largely attributed to the lower ...