Epitaxial growth of cubic silicon carbide on silicon using hot filament chemical vapor deposition

Hens, Philip; Brow, Ryan; Robinson, Hannah; Cromar, M. W.; Zeghbroeck, B. Van

doi:10.1016/j.tsf.2017.02.024

Cited by 12 publications

(13 citation statements)

References 6 publications

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“…These results are in agreement with the typical pyramidal shape pits of the SiC/Si(100) interface already reported in the literature. ,,,, The observed defects have an interface area density of about 50% displaying the same organization as the typical defects of Si(100) surfaces annealed in bad vacuum conditions. We expect their presence already before the codeposition procedure, as reported in the literature. , …”

Section: Resultssupporting

confidence: 61%

“…We expect their presence already before the codeposition procedure, as reported in the literature. 47,55 Concerning the samples S2_1200_70 and S2_1200_100 grown at 1200 K, both show a long-range order at the 3C-SiC surface, as confirmed by LEED (Table 1) and by the presence of surface electronic states in the combined UPS-IPS spectra (Figure 1). The topmost layers of the films have different LEED patterns and surface electronic states, typical of 3C-SiC(100) terminated surfaces: the c(2 × 2) pattern corresponds to a C-terminated surface, while 3 × 2 corresponds to a Si-terminated surface.…”

Section: ■ Results and Discussionmentioning

confidence: 60%

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Tuning 3C-SiC(100)/Si(100) Heterostructure Interface Quality

Pedio

Magnano

Moras

et al. 2022

Crystal Growth & Design

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We report a systematic spectroscopic and structural investigation of 3C-silicon carbide (3C-SiC) films grown on Si(100)-(2 × 1) by codeposition of C 60 molecules and Si atoms in ultrahigh-vacuum conditions. This work focuses on reducing the macroscopic defects formed at the interface in Si-SiC heterojunctions. A wide range of parameters influence the growth process, including the substrate deposition temperature, the relative effusion fluxes of C 60 and Si, and the clean Si(100) surface order. By adjusting the Si and C 60 deposition rates, it is possible to reduce the Si atom diffusion from the substrate and control both the surface morphology and the specific formation of the Crich c(2 × 2) or Si-rich 3 × 2 ordered surfaces. Our results show that the growth of 3C-SiC on flat and good quality Si substrates is a crucial and necessary starting point to obtaining good quality 3C-SiC/Si interfaces with a minimum number of defects.

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Section: Resultssupporting

confidence: 61%

Section: ■ Results and Discussionmentioning

confidence: 60%

Tuning 3C-SiC(100)/Si(100) Heterostructure Interface Quality

Pedio

Magnano

Moras

et al. 2022

Crystal Growth & Design

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“…Moreover, the as-made SiC is usually bulk crystal with relatively large thickness and poor quality, which prevent it from having high device performance. On the other hand, the conventional CVD growth of SiC is performed at a very high temperature ranging from 1400 to 1600 °C, which requires special apparatus and thus restricting industrial productions. − Currently, a facile and direct approach for the growth of large-scale 2D or ultrathin single-crystal SiC is highly desired to be developed.…”

Section: Introductionmentioning

confidence: 99%

Graphene-Induced in Situ Growth of Monolayer and Bilayer 2D SiC Crystals Toward High-Temperature Electronics

Geng

et al. 2019

ACS Appl. Mater. Interfaces

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A reproducible graphene-induced in situ process is demonstrated for the first time for growing large-scale monolayer and bilayer cubic silicon carbide (SiC) crystals on a liquid Cu surface by chemical vapor deposition (CVD) method. Precise control over the morphology of SiC crystals is further realized by modulating growth conditions, thus leading to the formation of several shaped SiC crystals ranging from triangular, rectangular, pentagonal, and even to hexagonal kind. Simulations based on density functional theory are carried out to elucidate the growth mechanism of SiC flakes with various morphologies, which are in striking consistency with experimental observations. In the liquid Cu-assisted CVD system, growth temperature (∼1100 °C) enables sublimation and deposition of silicon oxide (SiO2) derived from quartz tube, while liquid Cu facilitates preformation of graphene originated from methane. The SiO2 and graphene, grown and reacted in situ in the CVD process, are served as the silicon and carbon source for the cubic SiC crystals, respectively. Moreover, the gradual transformation process from SiO2 particles to SiC flakes is directly observed, with several middle stages clearly displayed. The direct in situ growth of SiC crystals offers a novel method for scaled production of SiC crystals and is beneficial to understand its growth mechanism, and thus push forward the way to develop high-temperature and high-frequency electronic devices.

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“…To date, two technologies, heteroepitaxy growth and wafer bonding, can be utilized to realize the Si/SiC heterojunction devices [13][14][15][16][17]. Both technologies will generate dislocations and defects at the heterointerface owing to the 19.3% lattice mismatch value between the Si and SiC.…”

Section: Heterointerface Charge Analysismentioning

confidence: 99%

A Novel Low On−State Resistance Si/4H−SiC Heterojunction VDMOS with Electron Tunneling Layer Based on a Discussion of the Hetero−Transfer Mechanism

Chen

Zhang

Zhou³

et al. 2023

Crystals

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In this study, we propose a novel silicon (Si)/silicon carbide (4H−SiC) heterojunction vertical double−diffused MOSFET with an electron tunneling layer (ETL) (HT−VDMOS), which improves the specific on−state resistance (RON), and examine the hetero−transfer mechanism by simulation. In this structure, the high channel mobility and high breakdown voltage (BV) are obtained simultaneously with the Si channel and the SiC drift region. The heavy doping ETL on the 4H−SiC side of the heterointerface leads to a low heterointerface resistance (RH), while the RH in H−VDMOS is extremely high due to the high heterointerface barrier. The higher carrier concentration of the 4H−SiC surface can significantly reduce the width of the heterointerface barrier, which is demonstrated by the comparison of the conductor energy bands of the proposed HT−VDMOS and the general Si/SiC heterojunction VDMOS (H−VDMOS), and the electron tunneling effect is significantly enhanced, leading to a higher tunneling current. As a result, a significantly improved trade−off between RON and BV is achieved. With similar BV values (approximately 1525V), the RON of the HT−VDMOS is 88% and 65.75% lower than that of H−VDMOS and the conventional SiC VDMOS, respectively.

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Epitaxial growth of cubic silicon carbide on silicon using hot filament chemical vapor deposition

Cited by 12 publications

References 6 publications

Tuning 3C-SiC(100)/Si(100) Heterostructure Interface Quality

Tuning 3C-SiC(100)/Si(100) Heterostructure Interface Quality

Graphene-Induced in Situ Growth of Monolayer and Bilayer 2D SiC Crystals Toward High-Temperature Electronics

A Novel Low On−State Resistance Si/4H−SiC Heterojunction VDMOS with Electron Tunneling Layer Based on a Discussion of the Hetero−Transfer Mechanism

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