ePlace-MS: Electrostatics-Based Placement for Mixed-Size Circuits

Abstract

Abstract-We propose eP lace-M S, an electrostatics based placement algorithm for large-scale mixed-size circuits. ePlace-MS is generalized, flat, analytic and nonlinear. The density modeling method eDensity is extended to handle the mixedsize placement. We conduct detailed analysis on the correctness of the gradient formulation and the numerical solution, as well as the rationale of direct-current removal and the advantages over prior density functions. Nesterov's method is used as the nonlinear solver, which shows high yet stable performance over mixed-size circuits. The steplength as the inverse of Lipschitz constant of the gradient function, while we develop a backtracking method to prevent overestimation. An approximated nonlinear preconditioner is developed to minimize the topological and physical differences between large macros and standard cells. Besides, we devise a simulated annealer to legalize the layout of macros and use a second-phase global placement to reoptimize the standard cell layout. All the above innovations are integrated into our mixed-size placement prototype ePlace-MS, which outperforms all the related works in literature with better quality and efficiency. Compared to the leading-edge mixed-size placer NTUplace3 [13], ePlace-MS produces up to 22.98% and on average 8.22% shorter wirelength over all the sixteen modern mixed-size (MMS) benchmark circuits with the same runtime.

Circular-contour-based obstacle-aware macro placement

“…It should be noted that the one-stage mixed-size placers such as the work [10] and ePlace-MS [16] do not handle big pre-placed macros (obstacles) and do not consider routability, which are the core issues addressed in this paper. Therefore, we just listed results of the work [10] for reference.…”

“…The works [7,8,10] classify mixed-size placement algorithms into three types: (1) One-stage mixed-size placement places macros and standard cells simultaneously; SimPL [11], ComPLx [12], MAPLE [13], mPL6 [3], NTUplace3 [6], Hsu and Chang [10], and ePlace-MS [16] belong to this type. (2) Constructive mixed-size placement places macros constructively, free of overlaps; Capo [2] and FLOP [20] are two examples; (3) Three-stage mixed-size placement divides the mixed-size placement into the following three stages: placement prototyping, macro placement, and standard-cell placement; XDP [9], CG [4], MP-tree [7] and CP-tree [8] belong to this type.…”

DREAMPlace 3.0

“…ePlace-series placers [22][23][24][25] are among a state-of-the-art family of placement algorithms that model the layout and netlist as a unified electrostatic system. It approximates the non-differentiable halfperimeter wirelength (HPWL) with a weighted-average wirelength (WA) model originally proposed by [28],…”

“…There are also many placers that tackle the classic placement problem without considering the region constraints . Recently, ePlace-series [22][23][24][25][26] were proposed to model the cells as charges and cast the placement problem as a wirelength minimization task with electric potential energy constraints. However, the current unified electrostatic field is agnostic to region constraints and fails to support many advanced designs [1,27].…”

Simulation Algorithms With Exponential Integration for Time-Domain Analysis of Large-Scale Power Delivery Networks

“…M ODERN VLSI design verification relies heavily on the analysis of power delivery network (PDN) to estimate power supply noises [1]- [8]. The performance of power delivery network highly impacts on the quality of global, detailed and mixed-size placement [9]- [11], clock tree synthesis [12], global and detailed routing [13], as well as timing [14] and power optimization. Lowering supply voltages, increasing current densities as well as tight design margins demand more accurate large-scale PDN simulation.…”