Equalization and clock recovery for a 2.5-10Gb/s 2-PAM/4-PAM backplane transceiver cell

Abstract

The backplane environment presents a serious challenge to signaling rates above 5Gb/s. Previous 10Gb/s transceivers [1] are not designed for this harsh environment. In the raw single bit response of Fig. 4.6.1, a single 200ps pulse undergoes serious loss and dispersion and initiates reflections that may be a significant percentage of an equalized eye. Figure 4.6.1 (inset) shows a zoom-in of the reflections plotted on a scale equivalent to a single 4-PAM equalized eye. The total usable amplitude after equalization is slightly smaller than 3d which is the distance between the peak sample point and the next sample point of the raw pulse response. While the use of multiple signaling levels and transmit equalization help minimize the effects of dispersion [2,3], transmit-only equalization is an expensive way to combat the effect of reflections which are more destructive to multi-level signaling. Decision feedback-based receive equalization (DFE) is effective when dealing with configuration dependent reflections. The design of both transmit and receive equalizers and clock recovery circuits are described for operation in this type of backplane environment.Since dispersion is a function of many properties in backplanes, flexibility in the transmit equalizer, both in number of taps and their settings is highly desirable. One completely flexible approach involves the use of a digital filter and DAC [4], while the simplest approach is two-tap pre-emphasis [5]. Any technique must be evaluated for both additional insertion loss as well as for power and complexity.The five-tap merged differential transmitter/equalizer shown in Fig. 4.6.2 leverages the fact that the total transmitted current is limited to less than the sum of the maximum taps to reduce pad parasitics. It achieves this by using large segments that can be individually allocated to any tap position. The transmit equalizer is partitioned into a shared section and a dedicated section. The shared section consists of 7 large sub-drivers, each driving 16i current, where each shared sub-driver can select from any of the 5 equalization tap streams A -E. The dedicated portion consists of five binary weighted drivers, one for each equalization tap, and each capable of driving up to 15i current. This combination of shared and dedicated drivers allows each equalization tap to have the same current range, 127i, and resolution, 1i, of a non-equalizing 7b transmitter with only 50% additional parasitic overhead. Comparatively, a 5-tap transmitter/equalizer with the same range and resolution implemented by replicating the primary driver has a 400% parasitic overhead. A pure digital filter and DAC implementation requires a FIR filter running at the symbol rate and consumes more than twice the power.For receive equalization, the linearity and high bandwidth of the transmission line environment were leveraged by adding and subtracting currents directly at the input pads. The receive equalizer is equivalent to a 1/5th scaled transmit equalizer. High-latency reflections are effective...

A 20Gb/s triple-mode (PAM-2, PAM-4, and duobinary) transmitter

“…Transmitters with feed forward equalization (FFE) are often employed in order to operate reliably over such channels at high data rates [1], [2]. However, due to transmit peak-power limitations imposed by shrinking CMOS power supplies, only incremental performance improvement is achieved by increasing transmitter equalization complexity past two or three taps [3].…”

“…Examples of high-speed serial I/O transmitters which implement these different modulation formats include [2], [4], [5]. The work of [2], [4] implements a transmitter which is compatible with PAM2 and PAM4 modulation, but does not support duobinary due to the absence of the precoder necessary to avoid error propagation.…”

“…The work of [2], [4] implements a transmitter which is compatible with PAM2 and PAM4 modulation, but does not support duobinary due to the absence of the precoder necessary to avoid error propagation. Custom designed transmitters for each modulation scheme are compared in [5], which implements the duobinary transmitter with a full-rate precoder.…”

A 10Gb/s transmitter with multi-tap FIR pre-emphasis in 0.18μm CMOS technology

“…ISI is the major factor limiting the maximum distance and data rate of backplane data transmission. Using a symbol-spaced FIR filter for preemphasis at transmit side is a popular technique for counteracting ISI [1,2,3]. Traditionally, the symbol-spaced data for a multi-tap FIR filter is generated by employing a single-edge-triggered D flip-flop (DFF) with full-rate clock retiming.…”

An adaptive 4-PAM decision-feedback equalizer for chip-to-chip signaling

“…This paper describes an adaptive decision-feedback equalizer ( D E ) design, implemented in the receiver, which avoids these problems. A DFE is an equalizer that uses the past decisions of the receiver and an estimate of the channel impulse response to create and subtract a replica of the IS1 from the current symbol [4][5] [6]. The LMS algorithm used in conventional adaptive DFEs requires an error signal to guide the adaptation.…”