Equivalence verification for NULL Convention Logic (NCL) circuits

Wijayasekara, Vidura; Srinivasan, Sudarshan K.; Smith, Scott C.

doi:10.1109/iccd.2014.6974681

Cited by 8 publications

(8 citation statements)

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“…The use of the combinational abstraction requires that the combinational blocks abstracted in the NCL and synchronous circuits are equivalent. This can be verified using techniques from [7].…”

Section: Abstraction Of Combinational Unitsmentioning

confidence: 85%

“…To elaborate, a verification check is required that checks that the abstraction function from Definition 3 is equivalent to the completion tree from the original circuit that is replaced. This can be verified using techniques from [7].…”

Section: Abstraction Of Completion Mechanismmentioning

confidence: 85%

“…The combinational multiplier circuit and the three completion trees in the MAC were abstracted away using our abstraction techniques. Combinational multiplier circuit can be verified independently using equivalence verification method for combinational circuits [7]. The benchmarks and verification proof obligations were specified using the satisfiability modulo theories library (SMT‐LIB) language [10] and were checked using the Yices Solver version 2.4.2 [11].…”

Section: Resultsmentioning

confidence: 99%

“…A very successful verification technology in the semiconductor industry is formal equivalence checking, where optimised circuits are checked for correctness against their original/parent counterparts. Wijayasekara et al [7] developed the first known formal verification methodology to check the equivalence of NCL circuits against their synchronous counterparts. However, as will be shown in the 'Results' section, efficiency and scalability of verification was quite limited.…”

mentioning

confidence: 99%

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Abstraction techniques to improve scalability of equivalence verification for NCL circuits

Wijayasekara

Rollie²,

Hodges³

et al. 2016

Electron. lett.

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Asynchronous NULL convention logic (NCL) circuits are dual-rail quasi-delay-insensitive circuits that have many applications in high radiation and extreme temperature fluctuation environments such as space exploration. Two abstraction techniques are proposed that can be used to drastically improve the efficiency and scalability of formal equivalence verification targeted at NCL circuits. The effectiveness of the abstraction techniques have been demonstrated using a number of multiply and accumulate circuit benchmarks.

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Section: Abstraction Of Combinational Unitsmentioning

confidence: 85%

Section: Abstraction Of Completion Mechanismmentioning

confidence: 85%

Section: Resultsmentioning

confidence: 99%

mentioning

confidence: 99%

See 2 more Smart Citations

Abstraction techniques to improve scalability of equivalence verification for NCL circuits

Wijayasekara

Rollie²,

Hodges³

et al. 2016

Electron. lett.

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“…There have also been several formal verification approaches to check safety and liveness of NCL circuits [8,9]; however, safety and liveness verification does not guarantee input completeness, which has to be verified independently.…”

mentioning

confidence: 99%

Automated verification of input completeness for NCL circuits

Srinivasan

Smith

2018

Electron. lett.

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An automated formal verification approach for ensuring input completeness of NULL Convention Logic (NCL) circuits is proposed. NCL circuits have the benefit that they can operate in extreme environments where traditional synchronous circuits fail due to significant fluctuations in circuit timing. Input completeness is a critical property to ensure correct functioning of NCL circuits in extreme environments and therefore is required to be verified. Note that an NCL circuit can be functionally correct and still not be input complete, which could cause the circuit to operate correctly under normal conditions, but malfunction only when the circuit timing is substantially changed (e.g. operating in a very hot or cold environment such as outer space).

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