Equivalent network synthesis for via holes discontinuities

Antonini, Giulio; Scogna, Antonio Ciccomancini; Orlandi, Antonio

doi:10.1109/tadvp.2002.807563

Cited by 32 publications

(17 citation statements)

References 24 publications

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“…Then by matching the Y/Z parameters of the template and the measured Y/Z parameters (e.g. matching their poles and zeros), we can determine the element values in the template [9]- [12].…”

Section: B Board and Package Modelingmentioning

confidence: 99%

Modeling and design for beyond-the-die power integrity

Shi

2010

2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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Abstract-Power integrity gains growing importance for integrated circuits in 45nm technology and beyond. This paper provides a tutorial of modeling and design for beyond the die power integrity.We explain the background of simultaneous switching noise (SSN) and its impacts on circuit designs. We discuss various models of different accuracy and complexity for the board, package and chip, and suggest how to select proper ones for board-package-chip co-simulation and co-design of SSN. We then review different design techniques to suppress SSN, including I/O planning and placement, decoupling capacitor allocation, package layer stacking and power/ground plane stapling.

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“…Then by matching the Y/Z parameters of the template and the measured Y/Z parameters (e.g. matching their poles and zeros), we can determine the element values in the template [9]- [12].…”

Section: B Board and Package Modelingmentioning

confidence: 99%

Modeling and design for beyond-the-die power integrity

Shi

2010

2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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“…5) can be extracted considering symmetry (Z 11 = Z 22 ) and reciprocity (Z 21 = Z 12 ) (Antonini, Scogna and Orlandi, 2002), (Heinrich and Dickmann, 2008):…”

Section: Extraction Of the Via Model Elementsmentioning

confidence: 99%

Coupling between Vias and the PCB Power-Bus

Heinrich

Dickmann

2009

Adv. Radio Sci.

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Abstract. In this paper, a method for the extraction of data for a through-hole vertical interconnect access (via) on a printed circuit board (PCB) is presented. It uses a matrix de-embedding algorithm and two-port theory to extract the elements of an assumed lumped via model. After that the influence of the via on the power-bus impedance and the coupling between the via and the power-bus are described using this model.

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“…In [6,7], the procedure for extracting the equivalent circuit of a via hole in a multilayered PCB is done as follows; a via hole is partitioned in three elementary structures: one for the top layer, one for the intermediate layer(s), and the last one for the bottom layer. Then, an equivalent circuit is obtained in the form of a two-port network for each elementary structure, where the elements of this two-port network depend on the via resistance (R via ), inductance (L via ), and capacitance (C via ); pad capacitance (C pad ), and interplanes capacitance (C ip ) values.…”

Section: Equivalent Circuit Extraction Technique For Differentiamentioning

confidence: 99%

“…Their approach, however, was only used for characterization of a single via hole and not for differential via holes. This article extends the equivalent circuit extraction technique, described in [6,7], for differential via holes characterization on a PCB, in a fast and accurate manner.…”

Section: Introductionmentioning

confidence: 99%