ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)
DOI: 10.1109/iccad.2003.1257627
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Equivalent waveform propagation for static timing analysis

Abstract: Abstract-This paper proposes a scheme that captures diverse input waveforms of CMOS gates for static timing analysis (STA). Conventionally latest arrival and transition times are calculated from the timings when a transient waveform goes across predetermined reference voltages. However, this method cannot accurately consider the impact of waveform shape on gate delay when crosstalk-induced nonmonotonic waveforms or inductance-dominant stepwise waveforms are injected. We propose a new timing analysis scheme cal… Show more

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Cited by 8 publications
(9 citation statements)
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“…5) Compute the waveform at the receiver end of the interconnect by using a reverse Laplace transform, which then becomes the input waveform at the fan-out gate. When the derived waveform shape is different from the shape assumed in the gate-delay model, the waveform is approximated [67].…”
Section: A Waveform Propagationmentioning
confidence: 99%
“…5) Compute the waveform at the receiver end of the interconnect by using a reverse Laplace transform, which then becomes the input waveform at the fan-out gate. When the derived waveform shape is different from the shape assumed in the gate-delay model, the waveform is approximated [67].…”
Section: A Waveform Propagationmentioning
confidence: 99%
“…Traditional library cell characterization that accurately covers a wide range of operating voltages can be prohibitively time consuming. In [3]- [4] the common voltage-based cell timing analyzers are reviewed and their shortcomings are highlighted.…”
Section: Introductionmentioning
confidence: 99%
“…Interested reader may refer to references [3]- [4] that extensively explain the various voltage-based cell delay models and their shortcomings and strengths. Two recently developed approaches, i.e., equation-based and current-based techniques, contend to replace voltage-based lookup tables.…”
Section: Introductionmentioning
confidence: 99%
“…In [3]- [4] the common voltagebased cell timing analyzers are reviewed and their shortcomings are highlighted. In addition to being inefficient in accurately considering the impact of the shape of the noisy waveform, the voltage-based timing analysis tools are inefficient in low power design styles that incorporate two or more logic "islands", each running at a different operating voltage.…”
Section: Introductionmentioning
confidence: 99%
“…Interested reader may refer to references [3]- [4] that extensively review the various voltage-based cell timing analyzers and discusses their shortcomings and strengths.…”
Section: Introductionmentioning
confidence: 99%