ERCBench: An Open-Source Benchmark Suite for Embedded and Reconfigurable Computing

Chang, Daniel W.; Jenkins, Christipher; Garcia, Philip; Gilani, Syed Zohaib; Aguilera, Paula; Nagarajan, Aishwarya; Anderson, Michael J.; Kenny, Matthew A.; Bauer, Sean; Schulte, Michael; Compton, Katherine

doi:10.1109/fpl.2010.85

Cited by 23 publications

(12 citation statements)

References 18 publications

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“…We use SPEC 2006 CPU benchmarks and CUDA GPGPU benchmarks from Nvidia CUDA SDK, Rodinia [Che et al 2009], Parboil [The IMPACT Research Group, UIUC], and ERCBench [Chang et al 2010]. For the CPU workloads, Pinpoint [Patil et al 2004] was used to select a representative simulation region with the reference input set.…”

Section: Benchmarksmentioning

confidence: 99%

Adaptive virtual channel partitioning for network-on-chip in heterogeneous architectures

Lee

Kim

et al. 2013

ACM Trans. Des. Autom. Electron. Syst.

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Current heterogeneous chip-multiprocessors (CMPs) integrate a GPU architecture on a die. However, the heterogeneity of this architecture inevitably exerts different pressures on shared resource management due to differing characteristics of CPU and GPU cores. We consider how to efficiently share on-chip resources between cores within the heterogeneous system, in particular the on-chip network. Heterogeneous architectures use an on-chip interconnection network to access shared resources such as last-level cache tiles and memory controllers, and this type of on-chip network will have a significant impact on performance.In this article, we propose a feedback-directed virtual channel partitioning (VCP) mechanism for on-chip routers to effectively share network bandwidth between CPU and GPU cores in a heterogeneous architecture. VCP dedicates a few virtual channels to CPU and GPU applications with separate injection queues. The proposed mechanism balances on-chip network bandwidth for applications running on CPU and GPU cores by adaptively choosing the best partitioning configuration. As a result, our mechanism improves system throughput by 15% over the baseline across 39 heterogeneous workloads.

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Section: Benchmarksmentioning

confidence: 99%

Adaptive virtual channel partitioning for network-on-chip in heterogeneous architectures

Lee

Kim

et al. 2013

ACM Trans. Des. Autom. Electron. Syst.

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“…We use a wide variety of workloads including PARSEC [16], UHPC challenge benchmarks [13], [15], Biobench [12] and ERCBench [19]. These benchmarks cover a wide range of application domains such as financial analysis, computer vision, genetic algorithms, physics simulation, data mining, streaming applications, graph algorithms, decision and search algorithms and signal processing.…”

Section: A Workloadsmentioning

confidence: 99%

Systematic evaluation of workload clustering for extremely energy-efficient architectures

Guha

Zhang

Rasool

et al. 2013

SIGARCH Comput. Archit. News

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Chip power consumption has reached its limits, leading to the flattening of single-core performance. We propose the 10x10 processor, a federated heterogeneous multi-core architecture, where each core is an ensemble of u-engines (micro-engines, similar to accelerators) specialized for different workload groups to achieve dramatically higher energy efficiency. The u-engines collectively target the entire general-purpose workload space.The problem we study in this article is selecting the set of workloads that each u-engine should be customized for. For this problem we study the computation structure of a wide variety of workloads and cluster together workloads with similar computation structures, the idea being that each u-engine will be customized for the compute structures exhibited by a particular cluster. The constraint on this problem is the silicon budget of a processor. Lower silicon budgets accommodate fewer uengines and require individual u-engines to target larger segments of the workload space which leads to lower energy efficiency benefits from customization, because there is more variation among the compute structures making up each cluster. Therefore, we also study how workload coverage and benefit can be maximized for a given silicon budget.We study a broad general-purpose workload that includes 34 codes from 6 benchmark suites, identifying the most frequent functions, and clustering them based on two sets of instruction usage features (high-resolution and low-resolution) into 8, 16, 32, 64, 128 clusters respectively. We develop abstract metrics (coverage and weighted customization benefit) to evaluate the clusters. We show significant potential payoffs with four benefit models: 2-3x (square root model), 4-10x (linear model), 12-24x (quadratic model), and 22-26x (cubic model).

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“…For our evaluation we use applications from the Mediabench [12], Mediabench II [13], Parboil [14], and ERCBench [15] benchmark suites. We choose four multimedia applications, one cryptographic application, and one scheduling application that are representative of typical embedded systems applications ( Table 2).…”

Section: Benchmarksmentioning

confidence: 99%

Energy-efficient reconfigurable cache architectures for accelerator-enabled embedded systems

Farmahini-Farahani

Kim

Morrow

2014

2014 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

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High-performance embedded systems often include one or more embedded processors tightly coupled with more specialized accelerators. These accelerators improve both performance and energy efficiency because they are specialized for specific (or specific classes of) computations. Data communication between the accelerator and memory, however, is a potential bottleneck for both performance and energyefficiency. In this paper, we compare and evaluate, for the first time, the impact of L1 data cache design on performance and energy consumption of embedded processor-accelerator systems with shared memory. For this evaluation, we consider data cache design parameters such as size, associativity, and port count, as well as L1 cache sharing between the processor and accelerator. We demonstrate the potential of configurable caches to exploit diversity in cache requirements across hybrid software/hardware applications to significantly improve energy-efficiency while maintaining high performance. Guided by these studies, we propose two techniques for improving energy-efficiency of the cache hierarchy in processoraccelerator systems. The first technique adds configurability to the accelerator-cache interface to allow the accelerator to either share the processor's L1 data cache or use its own private L1 cache. The second technique modifies the L1 cache structure to provide a configurable tradeoff between bandwidth (number of ports) and capacity. Our simulation results show that the first and second techniques improve cache hierarchy energy-efficiency by up to 64% and 33%, respectively, over that of non-configurable caches. 211978-1-4799-3606

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ERCBench: An Open-Source Benchmark Suite for Embedded and Reconfigurable Computing

Cited by 23 publications

References 18 publications

Adaptive virtual channel partitioning for network-on-chip in heterogeneous architectures

Adaptive virtual channel partitioning for network-on-chip in heterogeneous architectures

Systematic evaluation of workload clustering for extremely energy-efficient architectures

Energy-efficient reconfigurable cache architectures for accelerator-enabled embedded systems

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