2013
DOI: 10.1002/jnm.1881
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Error bounds for reduction of multi‐port resistor networks

Abstract: SUMMARYThe interconnect layouts of chips can be modeled by large resistor networks. In order to be able to speed up simulations of such large networks, reduction techniques are applied to reduce the size of the networks. For some class of networks, an existing reduction strategy does not provide sufficient reduction in terms of the number of resistors appearing in the final network. In this paper we propose an approach for obtaining a further reduction in the amount of resistors. The suggested approach improve… Show more

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Cited by 2 publications
(4 citation statements)
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“…where V is an orthogonal matrix that diagonalizes the matrixL e in (18). Again using the Woodbury inversion formula, we find that the inverse of I + T T T is given by I − T (I + T T T ) −1 T T .…”
Section: B T Y Ijmentioning
confidence: 91%
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“…where V is an orthogonal matrix that diagonalizes the matrixL e in (18). Again using the Woodbury inversion formula, we find that the inverse of I + T T T is given by I − T (I + T T T ) −1 T T .…”
Section: B T Y Ijmentioning
confidence: 91%
“…For resistor networks with scalar agent dynamics, the problem of model reduction by edge-removal was studied in [17] and [18].…”
Section: Introductionmentioning
confidence: 99%
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