Error Resilient GPU Accelerated Image Processing for Space Applications

Davidson, R. J. L.; Bridges, C. P.

doi:10.1109/tpds.2018.2812853

Cited by 30 publications

(18 citation statements)

References 16 publications

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“…It is possible to see that the ARTICo 3 -based HyLoC compressor renders results in the range of the rest of implementations, being only 3.2× slower (considering actual throughput values) than the fastest solution but flexible at run time, a unique feature of this work. The GPU-based implementation presented in [18] is the only one that also uses input image partitioning (referred to as tiling). However, the implemented partitioning scheme is the strip-based one, and the execution is performed using a fixed number of processing elements (GPUs cannot dynamically change its computing resources).…”

Section: Resultsmentioning

confidence: 99%

Scalable Hardware-Based On-Board Processing for Run-Time Adaptive Lossless Hyperspectral Compression

et al. 2019

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Hyperspectral data processing is a computationally intensive task that is usually performed in high-performance computing clusters. However, in remote sensing scenarios, where communications are expensive, a compression stage is required at the edge of data acquisition before transmitting information to ground stations for further processing. Moreover, hyperspectral image compressors need to meet minimum performance and energy-efficiency levels to cope with the real-time requirements imposed by the sensors and the available power budget. Hence, they are usually implemented as dedicated hardware accelerators in expensive space-grade electronic devices. In recent years though, these devices have started to coexist with low-cost commercial alternatives in which unconventional techniques, such as run-time hardware reconfiguration are evaluated within research-oriented space missions (e.g., CubeSats). In this paper, a run-time reconfigurable implementation of a low-complexity lossless hyperspectral compressor (i.e., CCSDS 123) on a commercial off-the-shelf device is presented. The proposed approach leverages an FPGA-based on-board processing architecture with a data-parallel execution model to transparently manage a configurable number of resource-efficient hardware cores, dynamically adapting both throughput and energy efficiency. The experimental results show that this solution is competitive when compared with the current state-of-theart hyperspectral compressors and that the impact of the parallelization scheme on the compression rate is acceptable when considering the improvements in terms of performance and energy consumption. Moreover, scalability tests prove that run-time adaptation of the compression throughput and energy efficiency can be achieved by modifying the number of hardware accelerators, a feature that can be useful in space scenarios, where requirements change over time (e.g., communication bandwidth or power budget). INDEX TERMS Data compression, dynamic and partial reconfiguration, FPGAs, high-performance embedded computing, hyperspectral images, on-board processing.

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Section: Resultsmentioning

confidence: 99%

Scalable Hardware-Based On-Board Processing for Run-Time Adaptive Lossless Hyperspectral Compression

et al. 2019

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“…The oracle is a tool that implements the post-conditions of the considered image processing application, that are the requisites for the usability of the inputs for the downstream end-user application. 1 The first stages of the design flow (namely fault injection and error simulation) are used to generate the training, validation and the test sets, used to design and evaluate the SC. The best α threshold value is chosen and several CNN architectures are trained and then evaluated by means of the validation set.…”

Section: Design Methodologymentioning

confidence: 99%

“…There are several classes of systems (e.g., automotive and aerospace) where safety-/mission-critical applications and non-critical applications coexist. For example, in the aerospace domain, the navigation system of a satellite is a mission-critical application while the payload processing applications are not [1]. On one hand, for mission-critical applications, it is mandatory to provide the desired level of reliability in the computation.…”

Section: Introductionmentioning

confidence: 99%

A Neural Network Based Fault Management Scheme for Reliable Image Processing

Biasielli

Bolchini

Cassano

et al. 2020

IEEE Trans. Comput.

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Traditional reliability approaches introduce relevant costs to achieve unconditional correctness during data processing. However, many application environments are inherently tolerant to a certain degree of inexactness or inaccuracy. In this paper, we focus on the practical scenario of image processing in space, a domain where faults are a threat, while the applications are inherently tolerant to a certain degree of errors. We first introduce the concept of usability of the processed image to relax the traditional requirement of unconditional correctness, and to limit the computational overheads related to reliability. We then introduce our new flexible and lightweight fault management methodology for inaccurate application environments. A key novelty of our scheme is the utilization of neural networks to reduce the costs associated with the occurrence and the detection of faults. Experiments on two aerospace image processing case studies show overall time savings of 14.89% and 34.72% for the two applications, respectively, as compared with the baseline classical Duplication with Comparison scheme.

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“…Image processing is today employed in a variety of safetyand mission-critical scenarios, where digital systems have to meet reliability requirements [1]. As an example let us consider a satellite hosting payload applications accelerated onto an FPGA; such a system operates in a harsh environment, where radiations may induce faults, e.g., Single Event Upset (SEU), in the circuitry that may lead to a failure of the running application [2].…”

Section: Introductionmentioning

confidence: 99%

Error Modeling for Image Processing Filters accelerated onto SRAM-based FPGAs

Bolchini

Cassano

Mazzeo

et al. 2020

2020 IEEE 26th International Symposium on on-Line Testing and Robust System Design (IOLTS)

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Image processing is today employed in a variety of application fields, including safety-and mission-critical ones. In these scenarios it is vital to carefully analyse the reliability of the designed system before deployment and, if necessary, to adopt specific hardening techniques. Two are the techniques generally employed: circuit-level fault injection and applicationlevel functional error simulation. In this paper we present a set of functional error models specific for a number of convolutionbased filters that are the basic building blocks for a wide range of image processing applications. The presented error models, derived through a number of circuit-level fault injection experiments, may be integrated into application-level functional error simulators, bridging the gap between the two strategies. The presented error models are the first step towards combining the accuracy of fault injection and the flexibility of error simulation into a widely adopted reliability analysis tool.

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Error Resilient GPU Accelerated Image Processing for Space Applications

Cited by 30 publications

References 16 publications

Scalable Hardware-Based On-Board Processing for Run-Time Adaptive Lossless Hyperspectral Compression

Scalable Hardware-Based On-Board Processing for Run-Time Adaptive Lossless Hyperspectral Compression

A Neural Network Based Fault Management Scheme for Reliable Image Processing

Error Modeling for Image Processing Filters accelerated onto SRAM-based FPGAs

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