ESD (Electrostatic Discharge) Protection Design for Nanoelectronics in CMOS Technology

Ker, Ming‐Dou

doi:10.1109/aspcas.2006.251127

Cited by 7 publications

(3 citation statements)

References 56 publications

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“…5 were input into relation (1) and equations (2)- (4) and their coefficients as well as the R-square values were determined by multiple regression analysis (Table III). For E model and thermochemical model, the electric field (E) term was also simplified to voltage (V).…”

Section: Resultsmentioning

confidence: 99%

“…By simulation of pulse voltage, the failure mechanisms of the circuit's breakdown could be investigated. Regarding the voltage pulse causing the damage in CMOS process, the major failures modes include burnt metal, junction damage, and dielectric breakdown [1,2]. The burnt metal failure is resulted from the overloading of metal route current.…”

Section: Introductionmentioning

confidence: 99%

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Temperature-dependent power-law model for submicron CMOS circuits EOS breakdown study

Tseng

Chang

2016

IEICE Electron. Express

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A temperature-dependent power-law model to simulate the pulsing EOS breakdown in CMOS integrated circuits (ICs) was proposed and evaluated in this study. It is a logarithm form of power-law model inversely related to the temperature. Fitting the results from the stressing of different commercial ICs with the grounded-gate NMOS (GGNMOS) ESD circuits by the electrical pulses indicated that the new model displayed comparable accuracy to the traditional E model/thermochemical model at constant/room temperature. When temperature changed, however, the new model had a better relationship in regression. The temperature-dependent power-law model could be used to evaluate the EOS window design of integrated circuits and be implemented into the components classification for the assembly line's quality control.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Temperature-dependent power-law model for submicron CMOS circuits EOS breakdown study

Tseng

Chang

2016

IEICE Electron. Express

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“…This defect mechanism occurs in between the channels of the gate oxide, the emitter, and collector. It is noted that the gate oxide degrades when the dielectric layer wears out due to a strong electric field of 10 MV/CM or above and electrostatic discharge [23]. The gate structure includes a thin oxide layer, which is used to isolate the gate from the MOS transistor, which due to a large voltage spike, emits an avalanche of electrons which causes an immediate breakdown [24].…”

Section: Failure Mechanism Overviewmentioning

confidence: 99%

Computationally Efficient, Real-Time, and Embeddable Prognostic Techniques for Power Electronics

Alghassi

Perinpanayagam

Samie

et al. 2015

IEEE Trans. Power Electron.

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Power electronics are increasingly important in new generation vehicles as critical safety mechanical subsystems are being replaced with more electronic components. Hence, it is vital that the health of these power electronic components is monitored for safety and reliability on a platform. The aim of this paper is to develop a prognostic approach for predicting the remaining useful life of power electronic components. The developed algorithms must also be embeddable and computationally efficient to support on-board real-time decision making. Current state-of-the-art prognostic algorithms, notably those based on Markov models, are computationally intensive and not applicable to real-time embedded applications. In this paper, an isolated-gate bipolar transistor (IGBT) is used as a case study for prognostic development. The proposed approach is developed by analyzing failure mechanisms and statistics of IGBT degradation data obtained from an accelerated aging experiment. The approach explores various probability distributions for modeling discrete degradation profiles of the IGBT component. This allows the stochastic degradation model to be efficiently simulated, in this particular example ∼1000 times more efficiently than Markov approaches. Index Terms-Isolated-gate bipolar transistor (IGBT), Monte-Carlo simulation (MCS), power electronics, prognostics, remaining useful life (RUL).

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Ultra-High Input Impedance Buffer for Dry or Capacitive Electrodes: Design and Characterization for Industry

Camós-Vidal,

Rosell-Ferrer

2023

IEEE Access

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ESD (Electrostatic Discharge) Protection Design for Nanoelectronics in CMOS Technology

Cited by 7 publications

References 56 publications

Temperature-dependent power-law model for submicron CMOS circuits EOS breakdown study

Temperature-dependent power-law model for submicron CMOS circuits EOS breakdown study

Computationally Efficient, Real-Time, and Embeddable Prognostic Techniques for Power Electronics

Ultra-High Input Impedance Buffer for Dry or Capacitive Electrodes: Design and Characterization for Industry

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