ESD protection for slew-rate-controlled output buffer in a 0.5μm CMOS SRAM technology

Abstract

ÐA new ESD protection design by using the well-coupled ®eld-oxide device (WCFOD) is proposed to protect the slew-rate-controlled output buer in a 0.5 mm P-well/N-substrate CMOS SRAM technology. The ESD transient voltage is coupled to the P-well of the ESD protection ®eld-oxide device through a parasitic capacitor to trigger on the bipolar action of the ®eld-oxide device. The ESD trigger voltage of the WCFOD can be lowered to below the snapback-breakdown voltage of the output NMOS transistor, so it provides eective ESD protection for the slew-rate-controlled output transistors without causing any degradation on the circuit performance. The coupling capacitor is made by inserting a poly layer right under the wire-bonding metal pad without the increase of layout area. A modi®ed WCFOD structure is also proposed for output ESD protection in deep-submicron CMOS technology with polycide or salicide processes. Three conventional output ESD protection designs with the series resistor, the double-diode structure, and the ®eld-oxide device, are also made for comparison. Five test chips with the same 256 K SRAM core but only dierent output ESD protection designs have been fabricated in a same wafer to practically verify the ESD protection eciency of this proposed WCFOD and modi®ed WCFOD structures.