Estimating routing congestion using probabilistic analysis

Abstract

Design routability is a major concern in the ASIC design flow, particularly with today's increasingly aggressive process technology nodes. Increased die areas, cell densities, routing layers, and net count all contribute to complex interconnect requirements, which can significantly deteriorate performance, and sometimes lead to unroutable solutions. Congestion analysis and optimization must be performed early in the design cycle to improve routability. This paper presents a congestion estimation algorithm for a placed netlist. We propose a net-based stochastic model for computing expected horizontal and vertical track usage, which considers routing blockages. The main advantages of this algorithm are accuracy and fast runtime. We show that the congestion estimated by this algorithm correlates well with postroute congestion, and show experimental results of subsequent congestion optimization based this algorithm.

An effective congestion driven placement framework

“…probabilistic global router to estimate the congestion in a region: The chip area is divided into small tiles, for each tile border the expected number of wires routed through this border is compared to the number of free routing tracks that cross the border. For example, the approaches in [3], [5], [7], [8], and [23] follow this idea. The algorithms differ mainly in the way they handle multi-terminal nets and blockages and in their probabilistic distributions for the interconnections.…”

A new and efficient congestion evaluation model in floorplanning: wire density control with twin binary trees

“…A floorplan is divided into a 2-dimensional grid structure and congestion is estimated at each grid. Similar approaches are also proposed in [4] and [5]. Although the above congestion evaluation models have been shown to be effective in reducing interconnect cost, their computational costs are very high.…”

On routing demand and congestion estimation for FPGAs

“…fGREP [6] is a new method that produces routing estimates on every channel in the FPGA. Lou's method [8], another new method, produces routing estimates on a region by region basis for ASICs. These two methods show great promise because they predict track usages on very fine level routing regions.…”

“…The following two sections briefly give the salient features of both the methods. More details can be found in [6] and [8].…”

“…al. [8] and compare it with our proposed methodology, fGREP [6]. We have implemented the two methods for a generic FPGA architecture and compare the performance, accuracy and usability of these estimates.…”