Estimating the Effective Pressure on Patterned Wafers during STI CMP

Abstract

Removal rate results obtained from a 150 mm Speedfam-IPEC 472 polisher, coupled with a proven removal rate model has allowed for the determination of effective pressure ͑i.e., the actual pressure exerted on the structures of a patterned wafer͒ during chemical mechanical planarization ͑CMP͒ of high-density plasma-filled shallow trench isolation ͑STI͒ wafers. Results showed that the ratio of derived effective pressure to applied wafer pressure was 2.2, 1.7, and 1.3 for 10, 50, and 90% density wafers, respectively. The relative consistency of these ratios indicates that the effective pressure experienced during polishing is not impacted by pattern density in a proportionate manner.It is critical to establish a problem-free approach for shallow trench isolation ͑STI͒ chemical mechanical planarization ͑CMP͒ because STI technology presents several advantages over the previous LOCOS ͑local oxidation of silicon͒ technology such as low junction capacitance, near zero-field encroachment, and exceptional latch-up immunity. 1 The general structure and property of materials used in STI technology has caused selectivity issues ͑i.e., oxide vs. nitride removal rates͒, nitride erosion, and trench oxide dishing. The aforementioned problems are generally associated with the overall material properties ͑i.e., Young's modulus͒ of the various STI layers, as well as variations of local removal rates resulting from the effects of patterned structures on the actual wafer pressure experienced during CMP.Patterned wafers pose uniformity problems due to inconsistent planarization times resulting from variations in die-level pattern density. For a set of identical CMP process conditions and wafers with no variations in pattern density ͑i.e., uniform and repeated patterns͒, more material is removed from a wafer with a lower pattern density than from one with a higher pattern density. When considering a wafer with significant variations in pattern density, typical polishing processes yield dramatic variations in local removal rate. 2 As a result, determining local and global removal rates becomes difficult, especially when considering that little is known about the contact mechanisms at the pad-wafer interface. This limitation reduces the capability of accurately determining the actual pressure experienced by the structures on the wafer surface.This study attempts to determine the effective pressure ͑i.e., the actual pressure exerted on the structures of a patterned wafer, also known as the envelop pressure͒ during STI CMP through a series of controlled temperature STI polishes. Using removal rate results in conjunction with a simplified Langmuir-Hinshelwood kinetics mechanism for material removal, this study derives the effective pressure experienced for STI wafers ranging in pattern densities of 10-90%. 3 ExperimentalPolishing.-All polishes were completed on a Speedfam-IPEC Avanti-472 polisher using 150 mm diameter wafers. The STI wafers used in the study had pattern densities of 10, 50, and 90% and exhibited no die-level pattern density va...

A Modeling Study on the Layout Impact of With-In-Die Thickness Range for STI CMP

“…The amount of over-polish will tend to increase these coefficients. All these results are in agreement with the previous reports in the literature based on test-mask results [1][2][3][4][5]. The unique contribution of this methodology is that it defines parameters based on a random/complex layout as opposed to test-masks which contain well defined lines and spaces with very specific widths and densities.…”

Cobalt “Buff Step” Chemical Mechanical Planarization

“…Simulation results.-To understand the non-Prestonian behavior observed in Figure 3 and to more fully characterize the polishing process, a two-step modified Langmuir-Hinshelwood model is used to simulate the silicon dioxide removal rate as well as the chemical and mechanical rate constants. 17,18 While this model has been successfully used in the past by our research team for copper, tungsten, titanium, ILD and STI applications using a variety of application-specific silicabased and ceria-based slurries and polyurethane pads, 6,12,[17][18][19][20][21][22][23] no previous work has been published on the possible utility of this model for cobalt "buff step" using a Fujibo H800-CZM pad and a slurry intended for this application. As such, we believe that our contribution to the field of polishing the dielectric surrounding cobalt plugs and local interconnects in MOL metallization is original.…”

A Modeling Study on the Layout Impact of With-In-Die Thickness Range for STI CMP

“…The WIDNU is perhaps the most difficult to deal with because it extends the furthest away from the CMP modulebeing primarily dictated by the design and layout. The design and the method of gap-fill proceeding CMP determines what the incoming profile looks like and this impacts the effective pressure applied to localized structures and ultimately the relative removal rate those structures experience (11). Significant reduction in WIDNU can be realized if CMP-based design rules can be implemented (12) and dummy structures be optimized (13)(14)(15).…”