Estimating the Fault Coverage of Functional Test Sequences Without Fault Simulation

Pomeranz, Irith; Parvathala, P.K.; Patil, S.

doi:10.1109/ats.2007.18

Cited by 19 publications

(9 citation statements)

References 23 publications

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“…Alternatively, it is possible to use test sequences that were generated as part of a simulation-based design verification process. In this case, either various metrics [11], [12], [13], [14] are suggested how to select the appropriate test sequences from the large verification test pool or selection procedures [16], [17] are proposed in order to improve the effectiveness of the existing functional test sequences.…”

Section: Related Workmentioning

confidence: 99%

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Black box delay fault models for non-scan sequential circuits

et al. 2018

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We presented nine new black box delay fault models for non-scan sequential circuits at the functional level, when the primary inputs and primary outputs are available only. We examined the suggested fault models in two stages. During the first stage of the experiment, we selected the best two fault models for further examination on the base of criterion proposed in the paper. During the second stage, we used the functional delay fault model and two black box delay fault models from the first stage for test selection. The comparison of fault coverages was carried out for transition faults. The obtained results demonstrate that transition fault coverages of tests selected based on proposed black box fault models are similar to coverages of tests selected based on functional delay fault model that uses the inner state of circuit.

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Section: Related Workmentioning

confidence: 99%

“…Pomeranz et al [11] described a stuck-at fault coverage metric based only on logic simulation of the gate level circuit. The metric is based on the set of states that the circuit traverses under the test sequence.…”

Section: Related Workmentioning

confidence: 99%

Black box delay fault models for non-scan sequential circuits

et al. 2018

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“…In former, we estimate the fault coverage by applying a set of test vectors and in latter, by measuring the number of detected faults for each test vector, we study how effective is the set of test vector in detecting faults. Much research has been done on fault coverage estimation using probabilistic distributions and fault modeling [14][3] [8] [20] [19] [4], and also test vector evaluation [11] [18] [23] [22] [5]. Most of This research was supported in part by a Grant from Cisco through the Silicon Valley Community Foundation.…”

Section: Introductionmentioning

confidence: 99%

Fast evaluation of test vector sets using a simulation-based statistical metric

Mirkhani

Abraham

2014

2014 IEEE 32nd VLSI Test Symposium (VTS)

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Evaluating the coverage of tests for large circuits is computationally very intensive, particularly for logic BIST, software-based self test and on-line test schemes. This has led to research into techniques for rapidly evaluating the coverage of proposed test. We introduce a new metric which is highly correlated with fault coverage measured by gate-level simulators. Based on this metric, we estimate the time when the fault coverage saturates. This is done with only one pass of simulation and it provides a measure of the effectiveness of the test sequence when applied to the circuit-under-test; additionally, the fault coverage can be estimated with a relatively small number of test vectors. Experimental results on the ISCAS'85 and ISCAS'89 benchmarks, and a RISC processor (OR1200), show an average error of 2.85% in the estimated fault coverage compared with the fault coverage from full fault simulation, with an average speedup over 8x for large circuits. I. INTRODUCTIONThe complexity of generating tests for faults, even in a combinational circuit, is much greater than that of evaluating the quality of a given test set, or fault grading [9]. When design-for-test features, such as Logic BIST, are incorporated into the design, fault grading the resulting large number of test vectors becomes a difficult problem. Additionally, major companies are resorting to cache-resident softwarebased self test (SBST) schemes in order to apply effective tests with shrinking technology feature sizes and V dd /frequency scaling [17] [6]. Furthermore, on-line test schemes for highly reliable systems require application-level test inputs while the system is operating in its functional mode. Fault grading both SBST and on-line test sequences requires sequential fault grading, which is significantly more difficult than grading tests for combinational circuits. In the case of using functional and random test vectors (versus ATPG-based scan test vectors) for large sequential circuits, it might take hours or days to fault grade a design with an acceptable fault coverage. Therefore, there has been considerable interest in developing techniques for quickly predicting or estimating the fault coverage in order to gauge the quality of a test sequence.Fault coverage estimation and test vector evaluation are closely related. In former, we estimate the fault coverage by applying a set of test vectors and in latter, by measuring the number of detected faults for each test vector, we study how effective is the set of test vector in detecting faults. Much research has been done on fault coverage estimation using probabilistic distributions and fault modeling [14][3][8][20][19][4], and also test vector evaluation [11][18][23][22][5]. Most of

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“…Another fault coverage metric is proposed in [9] In [2], fault coverage is estimated based on the output deviation from the expected value. It is based on the fact that, larger the probability that the test sequence deviates from the expected output, higher the chances of detecting faults.…”

Section: Introductionmentioning

confidence: 99%

Fault grading using Instruction-Execution graph

Vinutha

Singh

Matrosova

et al. 2010

2010 East-West Design &Amp; Test Symposium (EWDTS)

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Functional test sequences are used in testing to target faults that are not detected by structural test. However, evaluating the stuck-at fault coverage of the functional test sequence by the gate-level fault simulation can be very time consuming. To obtain a fast estimation of the fault coverage, we describe a metric to grade the test sequence using Instruction-Execution graph. The metric is based on the set of registers the circuit traverses under the test sequence. Using this information in combination with the observability and controllability of the register, the test sequence is graded. Experimental results on Parwan processor show the effectiveness of the metric in ranking the test sequence based on their fault coverage.

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Estimating the Fault Coverage of Functional Test Sequences Without Fault Simulation

Cited by 19 publications

References 23 publications

Black box delay fault models for non-scan sequential circuits

Black box delay fault models for non-scan sequential circuits

Fast evaluation of test vector sets using a simulation-based statistical metric

Fault grading using Instruction-Execution graph

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