Fast evaluation of test vector sets using a simulation-based statistical metric

Abstract

Evaluating the coverage of tests for large circuits is computationally very intensive, particularly for logic BIST, software-based self test and on-line test schemes. This has led to research into techniques for rapidly evaluating the coverage of proposed test. We introduce a new metric which is highly correlated with fault coverage measured by gate-level simulators. Based on this metric, we estimate the time when the fault coverage saturates. This is done with only one pass of simulation and it provides a measure of the effectiveness of the test sequence when applied to the circuit-under-test; additionally, the fault coverage can be estimated with a relatively small number of test vectors. Experimental results on the ISCAS'85 and ISCAS'89 benchmarks, and a RISC processor (OR1200), show an average error of 2.85% in the estimated fault coverage compared with the fault coverage from full fault simulation, with an average speedup over 8x for large circuits. I. INTRODUCTIONThe complexity of generating tests for faults, even in a combinational circuit, is much greater than that of evaluating the quality of a given test set, or fault grading [9]. When design-for-test features, such as Logic BIST, are incorporated into the design, fault grading the resulting large number of test vectors becomes a difficult problem. Additionally, major companies are resorting to cache-resident softwarebased self test (SBST) schemes in order to apply effective tests with shrinking technology feature sizes and V dd /frequency scaling [17] [6]. Furthermore, on-line test schemes for highly reliable systems require application-level test inputs while the system is operating in its functional mode. Fault grading both SBST and on-line test sequences requires sequential fault grading, which is significantly more difficult than grading tests for combinational circuits. In the case of using functional and random test vectors (versus ATPG-based scan test vectors) for large sequential circuits, it might take hours or days to fault grade a design with an acceptable fault coverage. Therefore, there has been considerable interest in developing techniques for quickly predicting or estimating the fault coverage in order to gauge the quality of a test sequence.Fault coverage estimation and test vector evaluation are closely related. In former, we estimate the fault coverage by applying a set of test vectors and in latter, by measuring the number of detected faults for each test vector, we study how effective is the set of test vector in detecting faults. Much research has been done on fault coverage estimation using probabilistic distributions and fault modeling [14][3][8][20][19][4], and also test vector evaluation [11][18][23][22][5]. Most of

Improved Methods for Accurate Safety Analysis of Real-Life Systems

“…Ensuring sufficiency of the workloads used for fault injection based safety evaluation is an open problem. Other practical limitations of fault injection based techniques are also highlighted in recent works [8,9].…”