Estimating the SEU failure rate of designs implemented in FPGAs in presence of MCUs

Vurgaftman, I.; Bidarte, Unai; Gomez-Cornejo, Julen; Lázaro, Jesús; Astarloa, Armando

doi:10.1016/j.microrel.2017.08.003

Cited by 12 publications

(8 citation statements)

References 9 publications

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“…Let us assume that a task is exposed with given SERs, 𝜌 1 (i.e., the number of expected SBUs per bit per time unit), 𝜌 2 (2-bit event SER), …, 𝜌 𝑘 (𝑘-bit event SER). The values of 𝜌 𝑘 can be easily estimated for different devices using existing tools [10]. Therefore, following the general reliability formulation, the probability of an 𝑘-bit event occurring m times during the task execution (and, therefore, affecting totally 𝑚 • 𝑘 bits) is 1 :…”

Section: Reliability Model and Its Validationmentioning

confidence: 99%

“…These SERs have been expressed in terms of #events per Mbit per day (Table 2). However, other approaches [32] and tools [10] of calculating 𝜌 𝑘 can be used instead to obtain 𝑘-bit event SERs for other environmental conditions. In order to provide the SERs per bit per millisecond, the calculation of 𝜇 𝑘 in Eq.…”

Section: A) Experimental Setupmentioning

confidence: 99%

“…In contrast, fault injection approaches provide a higher level of controllability to where and how the fault is emulated. For example, the failure rate of FPGA-based designs has been estimated for both SBUs and MCUs by injecting faults on adjacent physically cells of the configuration memory [10]. Although these methods are useful for reliability estimation purposes, they incur into significant delays since the device must be accessed externally in order not to be intrusive.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Analytical reliability estimation of SRAM-based FPGA designs against single-bit and multiple-cell upsets

Ramezani

Clemente

Franco

2020

Reliability Engineering & System Safety

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Section: Reliability Model and Its Validationmentioning

confidence: 99%

Section: A) Experimental Setupmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Analytical reliability estimation of SRAM-based FPGA designs against single-bit and multiple-cell upsets

Ramezani

Clemente

Franco

2020

Reliability Engineering & System Safety

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“…FPGA juga diklaim lebih murah dari PLC, dari segi perangkat yang hanya berupa perangkat keras konvensional, dari segi pelaksanaan proses desain, verifikasi dan validasi yang lebih singkat sehingga dapat menekan biaya operasional pada pengujian perangkat lunak [7,8]. Penggunaan FPGA pada reaktor riset sebelumnya digunakan untuk sistem pemantauan, dengan pertimbangan response time yang baik untuk real time monitoring [9].…”

Section: Pendahuluanunclassified

Kajian Implementasi Field Programmable Gate Array untuk Rencana Modernisasi Sistem Proteksi Reaktor

Maerani

Suryono

Santoso

et al. 2020

Jurnal Pengembangan Energi Nuklir

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Penggunaan Field Programmable Gate Array (FPGA) pada reaktor nuklir sudah dilakukan sejak 2016, terutama diaplikasikan pada perangkat Sistem Instrumentasi dan Kendali (SIK). FPGA sebelumnya sudah diujikan pada rancangan Sistem Proteksi Reaktor (SPR) dan Engineered Safety Feature – Component Control System (ESF-CCS) reaktor daya tipe APR1400. Dengan adanya rencana peremajaan SIK reaktor serbaguna G.A. Siwabessy (RSG-GAS) pada bagian SPR, diharapkan sistem berbasis FPGA juga dapat diimplementasikan pada reaktor riset. Dengan pertimbangan nilai ekonomi, keamanan dan juga keandalannya, FPGA yang berbasis perangkat keras dinilai akan lebih aman dari serangan jaringan, lebih murah dari Programmable Logic Controller (PLC) yang berbasis perangkat lunak dan proses verifikasi dan validasinya yang lebih sederhana. Untuk menjamin berlangsungnya performa SPR RSG-GAS, proses digitalisasi perangkat kendali tidak dapat dihindari dan sebaiknya dilakukan. Penelitian ini membahas siklus perancangan berbasis FPGA yang diawali dengan mengkaji dokumen panduan terkait sistem yang penting untuk keselamatan terutama yang berbasis FPGA agar dapat mengacu kepada persyaratan, baik untuk perancangan perangkat keras maupun perangkat lunak, proses reverse engineering hingga proses validasi. Hasil dari penelitian ini bertujuan agar pada proses desain dalam upaya peremajaan SPR RSG-GAS dapat mengikuti metode yang telah disyaratkan terkait perancangan SIK berbasis FPGA untuk reaktor riset, sehingga dapat mempermudah proses perolehan ijin dari badan pengawas tenaga nuklir untuk dapat dilakukan penggantian desain SPR berbasis FPGA.

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“…Other soft error studies related to multiple upsets include MBU effects on SRAM-based field-programmable gate arrays (FPGAs) [30], [31] and temporary multi-node upsets in combinational logic cells [32].…”

Section: Related Workmentioning

confidence: 99%

Modeling Application-Level Soft Error Effects for Single-Event Multi-Bit Upsets

Cho

Kwon

2019

IEEE Access

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Transient errors induced by radiations cause bit-flips in flip-flops (flip-flop soft errors).Modeling the error resilience level of a target system for flip-flop soft errors is a crucial step to achieve a costeffective error resilience solution. This step often requires a significant amount of time and effort for a large number of fault injection simulations. As technology scales, the required effort grows in a new dimension with the increased probability of multi-bit upsets (MBUs). In this work, we present a new estimation model that predicts the resulting error resilience levels for the flip-flop MBU cases. This estimation model only requires the measured soft error effects of the single-bit upset (SBU) cases. This model uses two strategies to address how multiple bit-flips that happen simultaneously in a system affects the outcome of application execution. We evaluate the accuracy level of the MBU estimation model using actual fault injection results on two different processor cores. The two main strategies in our estimation model improve the accuracy levels by more than 7×.

show abstract

Estimating the SEU failure rate of designs implemented in FPGAs in presence of MCUs

Cited by 12 publications

References 9 publications

Analytical reliability estimation of SRAM-based FPGA designs against single-bit and multiple-cell upsets

Analytical reliability estimation of SRAM-based FPGA designs against single-bit and multiple-cell upsets

Kajian Implementasi Field Programmable Gate Array untuk Rencana Modernisasi Sistem Proteksi Reaktor

Modeling Application-Level Soft Error Effects for Single-Event Multi-Bit Upsets

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