Estimation of average energy consumption of ripple-carry adder based on average length carry chains

Montalvo, Luis; Parhi, Keshab K.; Satyanarayana, J.H.

doi:10.1109/vlsisp.1996.558326

Cited by 12 publications

(6 citation statements)

References 8 publications

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“…Compared with [10], we present the SA with a Y -bit RCA instead of a W -bit RCA in the last stage, whose area is W Y times that of a Y -bit one's. Research on RCA areas that differ from bit width was conducted in [16]. Therefore, the proposed architecture uses the same number of multipliers, and the total number of adders is 1 − Y W less than [10].…”

Section: Comparison and Experiments Resultsmentioning

confidence: 99%

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A Pipelined Algorithm and Area-Efficient Architecture for Serial Real-Valued FFT

HongJi¹

2022

Preprint

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<div><div>In this brief, we present a novel pipelined architecture for real-valued fast Fourier transform (RFFT), which is dedicated to processing serial input data. </div><div> An optimized algorithm of the stage division for RFFT is proposed to achieve an area-efficient RFFT computing structure with full hardware utilization.</div><div> A single path butterfly (SBF) and a real rotator are merged into one processing element (PE) in each stage except the last stage to save latency and hardware resources.</div></div>

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Section: Comparison and Experiments Resultsmentioning

confidence: 99%

“…5(a). This circuit consists of four full adders (FAs), which are used to calculate the addition of 4-bit data [16]. Because the bit widths of real data are 16, we can add every four bits from low to high, shifting the 4-bit addition result.…”

Section: Table I Timing Diagram Of the Pe1mentioning

confidence: 99%

A Pipelined Algorithm and Area-Efficient Architecture for Serial Real-Valued FFT

HongJi¹

2022

Preprint

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“…5(a). This circuit consists of four full adders (FA), which are used to calculate the addition of 2-bits data [14]. Because the bit widths of the real data are 16, we can add every two bits from low to high, shifting the 2-bits addition result.…”

Section: Processing Elementsmentioning

confidence: 99%

A Pipelined Algorithm and Area-efficient Architecture for Serial Real-valued FFT

HongJi¹

2022

Preprint

View full text Add to dashboard Cite

<p>In this brief, we present a novel pipelined architecture for real-valued fast Fourier transform (RFFT), which is dedicated to processing serial input data. An optimized algorithm is proposed for stage division in RFFT to achieve an area-efficient RFFT computing structure with full hardware utilization. A single path butterfly and a real rotator are merged into one processing element (PE) in each stage, except the last stage, to reduce hardware resource utilization. In addition, a novel shift-adder is designed for N-point RFFT with W-bit signals, and a new data management method based on the PEs is proposed, which saves resources with a more regular flow graph.</p>

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“…This is not true for other architectures where the outputs are obtained by balanced binary trees like the Kogge and Stone. The activity caused by a carry propagation over k positions is proportional to k 2 /2 [MoPa96]. Thus the average activity is ""'".…”

Section: Activity Of the Rcamentioning

confidence: 99%

Spurious Transitions in Adder Circuits : Analytical Modelling and Simulations

Abou-Samra

Guyot

Laurent

1997

VLSI: Integrated Systems on Silicon

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Adder architectures are presented here by an unified formalism, and analysed from the delay, complexity and power consumption points of view. An analytical model for the power consumption is derived, assuming that it is proportional to the transition density [DHNT95]. The model is subsequently validated by simulation using a signal transition probabilities propagation tool [Cra89]. Finally, glitches are taken into account when transitions at the input of a cell are separated by one or more cell delays. A redundant to total power ratio is also derived.

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Estimation of average energy consumption of ripple-carry adder based on average length carry chains

Cited by 12 publications

References 8 publications

A Pipelined Algorithm and Area-Efficient Architecture for Serial Real-Valued FFT

A Pipelined Algorithm and Area-Efficient Architecture for Serial Real-Valued FFT

A Pipelined Algorithm and Area-efficient Architecture for Serial Real-valued FFT

Spurious Transitions in Adder Circuits : Analytical Modelling and Simulations

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