Estimation of circuit output measurements including statistically dependent parameters

SUMMARYMagnetoresistive random access memory (MRAM) is a leading candidate for future memory applications because it may provide compelling advantages by combining desirable attributes of SRAM, DRAM, and Flash. Process technology has recently scaled down to the nano-meter regime, which accordingly has resulted in lowering supply voltage, increasing short channel effect, and rapidly increasing process variation. MRAM is also affected by technology scaling, which significantly reduces the sensing margin. In this paper, several circuit design parameters, such as supply voltage, transistor size, and transistor gate voltage in the sensing circuit, are evaluated to discover the root causes of reduced sensing margin with technology scaling. The lowered supply voltage and lowered output resistance of the transistor, which occurs with technology scaling, are verified as the root causes of reduced sensing margin. It is also shown that increased process variation due to technology scaling aggravates the problem. A high supply voltage with power gating combined with optimized transistor size and gate voltage, and a power gating scheme using an IO device with an IO voltage are suggested as effective design solutions for reliably increasing the sensing margin in the presence of process variation.

Section: Process Variation Impact On the Sensing Margin Driven By Tecmentioning

confidence: 98%

Section: Process Variation Impact On the Sensing Margin Driven By Tecmentioning

confidence: 99%

Sensing margin trend with technology scaling in MRAM

Song

Kim

Kang

et al. 2011

“…A measurement‐based model was selected for the harmonic probabilistic PV model designed in our research. This model is based on the statistical characterisation of the real fundamental‐frequency PV current (PDF) and the statistical characterisation of PV harmonic currents (relative magnitude and phase angle) at different fundamental‐frequency current output intervals .…”

Section: Introductionmentioning

confidence: 99%

Harmonic modelling of PV systems for probabilistic harmonic load flow studies

Ruíz-Rodríguez

Hernández

Jurado

2014

Summary Probabilistic harmonic load flow (HLF) is currently enjoying renewed popularity. This is not surprising since in the near future, thousands of photovoltaic (PV) systems will be integrated into distribution systems. However, as yet, there is no model capable of explaining PV harmonic current behaviour in probabilistic HLF studies. To fill this gap, the harmonic modelling of PV systems proposed in this paper has three key points. First, it provides an effective model of the relationship between PV harmonic current emission and background harmonic voltages. Second, it statistically characterises PV harmonic currents (relative magnitude and phase angle) at different fundamental‐frequency current output intervals using historical time‐series data. In this statistical characterisation, the first fifth moments of each PV harmonic current are used to accurately approximate the raw probability density function (PDF) by means of the Legendre series. Finally, the third key point of this harmonic modelling is a method capable of determining the distribution functions of PV harmonic currents (absolute magnitude and phase angle), based on the statistical characterisation and a fundamental‐frequency probabilistic PV model. The numerical results obtained confirm the effectiveness of this PV model. Copyright © 2014 John Wiley & Sons, Ltd.

“…Moreover, the previous works have been proposed with the assumption of an ideal timing signal, and the process variation and glitch cases have not been fully considered. However, a design that considers the process variation becomes more important, especially in the deep submicron technology .…”

Section: Introductionmentioning

confidence: 99%

Dynamic mixed serial–parallel content addressable memory (DMSP CAM)

Kang

Kim

Yang

et al. 2011

SUMMARYA novel dynamic mixed serial-parallel content addressable memory (DMSP CAM) is proposed to achieve both low-power consumption and high performance. The replica circuits provide optimal timings to enable and disable the matchline charge transistor, which maximizes performance and minimizes leakage current, respectively. The DMSP CAM does not suffer from charge sharing in the serial stage and achieves high performance by removing the predischarge or precharge operation of the matchline before every comparison. To guarantee the robustness of the proposed scheme, a statistical design methodology is also applied. Using the 45-nm technology, the DMSP CAM achieves both energy saving and performance improvement, and thus over 53% energy-delay product reduction compared with the other serial-parallel mixed CAMs.