Estimation of wafer warpage profile during thermal processing in microlithography

Abstract

Wafer warpage is common in microelectronics processing. Warped wafers can affect device performance, reliability and linewidth control in various processing steps. We proposed in this paper an in-situ approach for estimating wafer warpage profile during the thermal processing steps in microlithography process. A programmable multizone thermal processing system is developed to demonstrate the approach. Early detection will minimize cost and processing time. Based on first principle thermal modeling and system identification techniques, we are able to estimate the profile of a warped wafer from available temperature measurements. Experimental results demonstrate the feasibility and repeatability of the approach. The proposed approach is applicable to other semiconductor substrates.

An inverse heat transfer method to provide near-isothermal surface for disc heaters used in microlithography

“…1(a)) of larger thermal mass [10,6]. This is true only when the natural convection effect from the top and side of the wafer substrate considered in [11][12][13] are eliminated. This can be done by providing a sealed container with proper size within which the baking is carried out.…”

“…Tan and Li [17] described a method for in situ estimation of the temperature sensor parameters, and proposed an algorithm for post-processing the sensor output to improve temperature measurement accuracy, to maintain stringent temperature conditions. Tay et al [13,18] developed an integrated bake/chill module with in situ temperature measurement capability for the baking of 300 mm silicon wafers, which gives better control over the substrate temperature. Three dimensional numerical simulation studies and experimental verification on a combination bake-chill station were done by Narasimhan et al [19] and Narasimhan and Ramanan [9], addressing the thermal agility capability of disc heaters to reach and maintain the wafer at different T SET values (for triggering various combinations of photo-resists on the wafer surface) and bring the temperature back to clean room temperature (by chilling/cooling process) within the prescribed bakechill cycle time of 150 s. Temperature uniformity of the heater surface was addressed only marginally.…”

A new in-situ warpage measurement of a wafer with speckle -free digital image correlation (DIC) method

“…One indirect method is to monitor the temperature profile of a conventional bake-plate during the thermal processing steps in microlithography [1]. The wafer warpage can be estimated in a reasonable range by empirical formulas [2]. To measure the wafer directly, a silicon shadow mask can be applied on the wafer, which have to contaminate the wafer and make the wafer sample nonrecyclable [3].…”

A new designed trench structure to reduce the wafer warpage in wafer level packaging process

“…Due to PI and Cu have very different coefficient of thermal expansion (CTE) with silicon substrate, large thermal stresses and wafer warpage will be induced after the thermal process. The wafer warpage may result in failure during packaging processes including automatic handling, photolithography, and wafer sawing [4][5][6]. As large diameter wafer is adopted and thinner wafer is required in 3D packaging, the warpage problem gets more serious.…”