ETAM++: extended transition activity measure for low power address bus designs

Lekatsas, H.; Henkel, J.

doi:10.1109/aspdac.2002.994895

Cited by 6 publications

(3 citation statements)

References 15 publications

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“…This approach has been extended to account for interwire capacitances [21], [31] and reliability issues [8], [9]. Bus encoding techniques have shown effectiveness in reducing power consumption, although the best results are generally achieved in specific environments such as address busses.…”

Section: B Related Work 1) Self-calibrationmentioning

confidence: 99%

A robust self-calibrating transmission scheme for on-chip networks

Worm

Ienne

Thiran

et al. 2005

IEEE Trans. VLSI Syst.

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Abstract-Systems-on-Chip (SoC) design involves several challenges, stemming from the extreme miniaturization of the physical features and from the large number of devices and wires on a chip. Since most SoCs are used within embedded systems, specific concerns are increasingly related to correct, reliable, and robust operation. We believe that in the future most SoCs will be assembled by using large-scale macro-cells and interconnected by means of on-chip networks. In this paper, we examine some physical properties of on-chip interconnect busses, with the goal of achieving fast, reliable, and low-energy communication. These objectives are reached by dynamically scaling down the voltage swing, while ensuring data integrity-in spite of the decreased signal to noise ratio-by means of encoding and retransmission schemes. In particular, we describe a closed-loop voltage swing controller that samples the error retransmission rate to determine the operational voltage swing. We present a control policy which achieves our goals with minimal complexity; such simplicity is demonstrated by implementing the policy in a synthesizable controller. Such a controller is an embodiment of a self-calibrating circuit that compensates for significant manufacturing parameter deviations and environmental variations. Experimental results show that energy savings amount up to 42%, while at the same time meeting performance requirements.Index Terms-Electrical parameter variations, interconnect for networks-on-chip, low-power systems-on-chip (SoC), self-calibrating designs, VLSI design methodology.

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Section: B Related Work 1) Self-calibrationmentioning

confidence: 99%

A robust self-calibrating transmission scheme for on-chip networks

Worm

Ienne

Thiran

et al. 2005

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

show abstract

“…This approach has been recently extended to account for interwire capacitances [13,9] and reliability issues [4]. Bus encoding techniques have shown effectiveness in reducing power consumption although the best results are generally achieved in specific environments such as address buses.…”

Section: Related Workmentioning

confidence: 99%

An adaptive low-power transmission scheme for on-chip networks

Worm

Ienne

Thiran

et al. 2002

Proceedings of the 15th International Symposium on System Synthesis - ISSS '02

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Systems-on-Chip (SoC) are evolving toward complex heterogeneous multiprocessors made of many predesigned macrocells or subsystems with application-specific interconnections. Intra-chip interconnects are thus becoming one of the central elements of SoC design and pose conflicting goals in terms of low energy per transmitted bit, guaranteed signal integrity, and ease of design. This work introduces and shows first results on a novel interconnect system which uses low-swing signalling, error detection codes, and a retransmission scheme; it minimises the interconnect voltage swing and frequency subject to workload requirements and S/N conditions. Simulation results show that tangible savings in energy can be attained while achieving at the same time more robustness to large variations in actual workload, noise, and technology quality (all quantities easily mispredicted in very complex systems and advanced technologies). It can be argued that traditional worst-case correct-by-design paradigm will be less and less applicable in future multibillion transistor SoC and deep sub-micron technologies; this work represents a first example towards robust adaptive designs.

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“…The methods in the first category [5][6][7][8][9] completely eliminate worst crosstalk coupling (a wire switching oppositely against its two neighboring wires) in order to get rid of crosstalk-induced delay. The methods in the second category [7,[10][11][12][13][14][15][16][17] re-arrange wiring layout for reducing coupling energy based on a priori knowledge about bus switching behavior. These methods can be best applied to an instruction address bus.…”

Section: Introductionmentioning

confidence: 99%

Coupling Reduction Analysis of Bus-Invert Coding

Lin

2005 IEEE International Symposium on Circuits and Systems

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Abstract-Theoretical analysis of bus-invert coding for reducing switching activity was previously investigated. In this paper we conduct a theoretical analysis of this method for coupling reduction. Closed-form formulas are derived to compute the number of couplings per bus transfer for a non-partitioned versus a partitioned bus. Our contribution complements the work done previously and helps establish a sound theoretical foundation for bus-invert coding.

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ETAM++: extended transition activity measure for low power address bus designs

Abstract: Interconnection networks in Systems-On-Chip

Cited by 6 publications

References 15 publications

A robust self-calibrating transmission scheme for on-chip networks

A robust self-calibrating transmission scheme for on-chip networks

An adaptive low-power transmission scheme for on-chip networks

Coupling Reduction Analysis of Bus-Invert Coding

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