EUROSERVER: Energy Efficient Node for European Micro-Servers

Durand, Yves; Carpenter, Paul; Adami, Stefano; Bilas, Angelos; Dutoit, Denis; Farcy, A.; Gaydadjiev, Georgi; Goodacre, John; Katevenis, Manolis; Marazakis, Manolis; Matúš, Emil; Mavroidis, Iakovos; Thomson, John

doi:10.1109/dsd.2014.15

Cited by 50 publications

(52 citation statements)

References 3 publications

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“…This chip does not offer hardware support for coherence between the chip's caches. Although it is not likely that the on-chip cache coherence will vanish in future systems [15], multi-core systems with coherence islands but no overall coherence are already existing [7]. However, to our knowledge there is no study on how those architectures can efficiently support the mentioned one-sided communication model.…”

Section: Introductionmentioning

confidence: 90%

Software-managed Cache Coherence for fast One-Sided Communication

Christgau

Schnor

2016

Proceedings of the 7th International Workshop on Programming Models and Applications for Multicores and Manycores

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The ongoing many-core design aims at core counts where cache coherence becomes a serious challenge. Therefore, this paper discusses how one-sided communication can be implemented on a non-cache coherent many-core CPU. The Intel SCC serves as an exemplary hardware architecture. The presented approach is based on software-managed cache coherence for MPI one-sided communication. The prototype implementation delivers a PUT performance of up to five times faster than the default message-based approach and reveals a reduction of the communication costs for the NPB 3D FFT by a factor of five. Further, the paper identifies drawbacks of the SCC's architecture and derives conclusions for future architectures.

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Section: Introductionmentioning

confidence: 90%

Software-managed Cache Coherence for fast One-Sided Communication

Christgau

Schnor

2016

Proceedings of the 7th International Workshop on Programming Models and Applications for Multicores and Manycores

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“…Various attempts to take advantage of mobile technology for increasing energy efficiency of HPC systems have also been taken in the recent past. The closest to our work are the EU Mont-Blanc project [16,17] and the COSA project [18,19], but several other examples can be found in the literature [20][21][22][23].…”

Section: Introduction and Related Workmentioning

confidence: 94%

Performance and Power Analysis of HPC Workloads on Heterogeneous Multi-Node Clusters

Mantovani

Calore

2018

JLPEA

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Performance analysis tools allow application developers to identify and characterize the inefficiencies that cause performance degradation in their codes, allowing for application optimizations. Due to the increasing interest in the High Performance Computing (HPC) community towards energy-efficiency issues, it is of paramount importance to be able to correlate performance and power figures within the same profiling and analysis tools. For this reason, we present a performance and energy-efficiency study aimed at demonstrating how a single tool can be used to collect most of the relevant metrics. In particular, we show how the same analysis techniques can be applicable on different architectures, analyzing the same HPC application on a high-end and a low-power cluster. The former cluster embeds Intel Haswell CPUs and NVIDIA K80 GPUs, while the latter is made up of NVIDIA Jetson TX1 boards, each hosting an Arm Cortex-A57 CPU and an NVIDIA Tegra X1 Maxwell GPU.

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“…EuroServer [9] [10] is a scale-out architecture with support for resource mutualization and sharing that uses integrated interconnects and 3D silicon integration technology to efficiently share resources. We take a different approach to improve the energy-efficiency of servers using FPGA-based reconfigurable accelerators [11] and new methods to program and share these accelerators.…”

Section: Background Workmentioning

confidence: 99%

NanoStreams: A Microserver Architecture for Real-Time Analytics on Fast Data Streams

Minhas

Russell

Kaloutsakis

et al. 2018

IEEE Trans. Multi-Scale Comp. Syst.

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Abstract-Ever increasing power consumption has created great interest in energy-efficient microserver architectures but they lack the computational, networking and storage power necessary to cope with real-time data analytics. We propose NanoStreams, an integrated architecture comprising an ARM-based microserver, coupled via a novel, low latency network interface, Nanowire, to a Analytics-on-Chip architecture implemented on Field Programmable Gate Array (FPGA) technology; the architecture comprises ARM cores for performing low latency transactional processing, integrated with programmable, energy efficient Nanocore processors for high-throughput streaming analytics. The paper outlines the complete system architecture, hardware level detail, compiler, network protocol, and programming environment. We present experiments with an industrial workload from the financial services sector, comparing a state-of-the-art server based on Intel Sandy Bridge processors, an ARM based Calxeda ECS-1000 microserver and ODROID XU3 node, with the NanoStreams microserver architecture. For end-to-end workload, the NanoStreams microserver achieves energy savings up to 10.7×, 5.87× and 5× compared to the Intel server, Calxeda microserver and ODROID node respectively.

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EUROSERVER: Energy Efficient Node for European Micro-Servers

Cited by 50 publications

References 3 publications

Software-managed Cache Coherence for fast One-Sided Communication

Software-managed Cache Coherence for fast One-Sided Communication

Performance and Power Analysis of HPC Workloads on Heterogeneous Multi-Node Clusters

NanoStreams: A Microserver Architecture for Real-Time Analytics on Fast Data Streams

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