EUV-CDA: Pattern shift aware critical density analysis for EUV mask layouts

Kagalwalla, Abde Ali; Lam, Michale; Adam, Kostas; Gupta, Puneet

doi:10.1109/aspdac.2014.6742882

Cited by 5 publications

(3 citation statements)

References 19 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…[16][17][18][22][23][24][25][26][27][28][29][30][31][32] An X and/or Y translation of the full-chip design relative to the blank is essential, however, additional degrees of freedom can also be considered, such as 90-degree rotations, micro-rotations 30 , and mask floorplanning 22,29 . Previous work have shown that microrotations and floorplanning provides only slight improvements for defect avoidance, despite the considerable complexity and resource allocation needed for HVM implementation.…”

Section: Experimental Verificationmentioning

confidence: 99%

Defect avoidance for EUV photomask readiness at the 7 nm node

Rankin

Narita

et al. 2016

SPIE Proceedings

View full text Add to dashboard Cite

Several challenges hinder extreme ultraviolet lithography (EUVL) photomask fabrication and its readiness for high volume manufacturing (HVM). The lack in availability of pristine defect-free blanks as well as the absence of a robust mask repair technique mandates defect mitigation through pattern shift for the production of defect-free photomasks. The work presented here provides a comprehensive look at pattern shift implementation to intersect EUV HVM for the 7 nm technology node. An empirical error budget to compensate for measurement variability and errors, based on the latest HVM inspection and write tool capabilities, is first established and then experimentally verified. The validated error budget is applied to 20 representative EUV blanks and pattern shift is performed on fully functional 7 nm node chip designs. The probability of defect-free masks is explored for various layers, including metal, contact, and gate cut layers. From these results, an assessment is made on the current viability of defect-free EUV masks and what is required to construct a complete defect-free EUV mask set.

show abstract

Section: Experimental Verificationmentioning

confidence: 99%

Defect avoidance for EUV photomask readiness at the 7 nm node

Rankin

Narita

et al. 2016

SPIE Proceedings

View full text Add to dashboard Cite

show abstract

“…Moreover, it has been shown that regular layout topologies like polysilicon layer tend to have lower mask yield than other layers [18]. Multi-layer defect avoidance methodology could utilize this fact by modifying the cost function appropriately to improve overall mask yield.…”

Section: Analysis For Multiple Layer Defect Avoidancementioning

confidence: 99%

Comprehensive defect avoidance framework for mitigating EUV mask defects

Kagalwalla

Gupta

2014

SPIE Proceedings

Self Cite

View full text Add to dashboard Cite

Defect avoidance methods are likely to play a key role in overcoming the challenge of mask blank defects in EUV lithography. In this work, we propose a novel EUV mask defect avoidance method. It is the first approach that allows exploring all the degrees of freedom available for defect avoidance (pattern shift, rotation and mask floorplanning). We model the defect avoidance problem as a global, non-convex optimization problem and then solve it using a combination of random walk and gradient descent. For a 8nm polysilicon layer of an ARM Cortex M0 layout, our method achieves 60% point better mask yield compared to prior art in defect avoidance for a 40-defect mask.

show abstract

“…Definition of prohibited region[13] While pattern shift is a sufficient defect avoidance measure for irregular patterns, it is ineffective for regular and unidirectional layout patterns. Kagalwalla et al provides a pattern shift aware critical density analysis where the results indicate that regular layouts are inadequate to tolerate mask defects through pattern shift [14]. This is due to linear and uniform change in defect location relative to mask pattern in pattern shift.…”

mentioning

confidence: 99%

Defect avoidance for extreme ultraviolet mask defects using intentional pattern deformation

Chae

Jonckheere

Gupta

2018

International Conference on Extreme Ultraviolet Lithography 2018

Self Cite

View full text Add to dashboard Cite

Extreme ultraviolet (EUV) lithography has been adopted as the next generation lithography solution to sub 10nm technology node with many companies claiming to be ready for production by late 2018. Despite the technology's maturity for production, EUV lithography still faces a number of challenges and mask blank defect is a major challenge. Defect avoidance method has been proposed to allow the mask defects to be tolerated by hiding them under the absorber patterns. By moving the design pattern relative to the defects' positions, more defects can be mitigated with the given absorber pattern. Past works have demonstrated usefulness of some degrees of freedom, however, pattern deformation has not been a subject of study. Hence, this thesis explores the extended benefits of utilizing pattern deformation, including linear asymmetric magnification and second-order deformation, by using new proposed method based on constraint programming.

show abstract

EUV-CDA: Pattern shift aware critical density analysis for EUV mask layouts

Cited by 5 publications

References 19 publications

Defect avoidance for EUV photomask readiness at the 7 nm node

Defect avoidance for EUV photomask readiness at the 7 nm node

Comprehensive defect avoidance framework for mitigating EUV mask defects

Defect avoidance for extreme ultraviolet mask defects using intentional pattern deformation

Contact Info

Product

Resources

About