EUV pattern shift compensation strategies

Abstract

EUV lithography is one of the hot candidates for the 22nm node. A well known phenomenon in EUV lithography is the impact of non-telecentricity and the mask topography on printing performance. Due to oblique illumination of the mask, layout, the printed features are shifted and biased on the wafer with respect to their target dimension up to several nanometers. This effect is inherent to EUV imaging systems. In order to maintain CDU, overlay and registration requirements, these effects need to be compensated for as part of the lithographic manufacturing process. Conventional compensation techniques, such as OPC compensation, significantly increase the complexity of the litho process.In this paper we discuss pattern shift, which is induced by mask-side non-telecentricity of the EUV ring field system. In particular, we show how the mask position relative to the focal plane of the projection system impacts pattern shift. It is shown that mask focus shift allows for a compensation of pattern shift, independent on angle of incidence, pattern type, pattern pitch, pattern orientation, and slit position. Thus it is seen that placement error is not an effect related to mask topography (not a shadowing effect) but arises purely from the mask non-telecentricity.A geometric interpretation of this effect is given and shown to be consistent with results of rigorous simulations. A method to simulate the shift of the mask focus position is briefly discussed. The mask focus shift for which the pattern shift vanishes in the aerial wafer image at best focus is determined using rigorous simulations. The amount of mask focus shift to compensate for the pattern shift is found to be approximately 136nm. This mask focus shift is then applied to investigate the through focus and dose behavior of the pattern shift in the resist. It is shown that the pattern shift is a function of wafer focus position and that this is a result of the image tilt in EUV systems. While the pattern shift is fully compensated at one wafer focus position, the shift at other positions is very small. The impact of the mask focus position on process window is investigated.

Defect avoidance for EUV photomask readiness at the 7 nm node

“…[16][17][18][22][23][24][25][26][27][28][29][30][31][32] An X and/or Y translation of the full-chip design relative to the blank is essential, however, additional degrees of freedom can also be considered, such as 90-degree rotations, micro-rotations 30 , and mask floorplanning 22,29 . Previous work have shown that microrotations and floorplanning provides only slight improvements for defect avoidance, despite the considerable complexity and resource allocation needed for HVM implementation.…”

Application of EUV resolution enhancement techniques (RET) to optimize and extend single exposure bi-directional patterning for 7nm and beyond logic designs

“…Thus, the image formation in EUV projection systems has specific challenges not found in immersion lithography. A number of authors have investigated EUV specific effects such as pattern placement error [1], assist feature placement and resulting Bossung tilt [2] and the stochastic nature of EUV imaging [3]. The recent publication by Hsu et al [4] demonstrated resolution enhancement techniques (RET) to address these EUV specific issues as part of the ASML Brion Tachyon NXE Source Mask Optimization (SMO) application.…”

3D mask effects of absorber geometry in EUV lithography systems

“…5,6 In EUVL systems all of these 3D mask effects are still present [7][8][9][10][11][12] in addition to image placement error due to the oblique illumination. 13,14 Of course the effects of mask topography are not lens aberrations, but drawing analogies to traditional aberration theory informs potential pupil plane compensation strategies.…”