Evaluating Coverage of Error Detection Logic for Soft Errors using Formal Methods

Krautz, Udo; Pflanz, Matthias; Jacobi, Christian; Tast, H.W.; Weber, Kai F.; Vierhaus, Heinrich Theodor

doi:10.1109/date.2006.244062

Cited by 41 publications

(24 citation statements)

References 13 publications

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“…Processor verification techniques focus on unmasking hardware design defects, as opposed to transient errors due to electrical disturbances or radiation. Soft-errors in Hardware: The techniques presented in [8] and [9] consider the effects of hardware transient errors (soft errors) on error-detection mechanisms im plemented in hardware. While these techniques are use ful for applications implemented as hardware circuits, it is not clear how the technique can be extended for rea soning about the effects of errors on programs.…”

Section: Related W Orkmentioning

confidence: 99%

SymPLFIED: Symbolic Program-Level Fault Injection and Error Detection Framework

Pattabiraman

Nakka²,

Kalbarczyk

et al. 2013

IEEE Trans. Comput.

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P ublic reportin g burden fo r this colle ctio n o f Inform ation Is e stim a te d to a verage 1 h o u r p e r re sponse , Including th e tim e fo r revie w in g instru ction s, searching existing da ta so u rce s, gathering a n d m a in ta in in g th e d a ta nee d e d , and com p le tin g a n d review ing th e colle ction o f info rm a tio n . S e nd com m e nt reg a rd in g th is burden estim a te or a n y o th e r asp e ct o f this collection o f in fo rm a tio n , in clu d in g su g g e stio n s fo r red u cin g th is b urden , to W a sh in g to n H e a d q u a rte rs S e rvices. D irectorate fo r in fo rm a tio n O pe ra tio n s and R eports, 1215 Je ffe rso n Davis H ighw ay, S u ite 1204, A rlin g to n , V A 222 02-4302, a n d to th e O ffice o f M a n a g e m e n t and Bu dget, P a perw ork R e d u ctio n P roject (0704-0188 ), W ashing ton , D C 20503

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Section: Related W Orkmentioning

confidence: 99%

SymPLFIED: Symbolic Program-Level Fault Injection and Error Detection Framework

Pattabiraman

Nakka²,

Kalbarczyk

et al. 2013

IEEE Trans. Comput.

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“…First approaches were proposed in [5,4]. Both methods apply tools for formal verification as a "black box".…”

Section: Introductionmentioning

confidence: 99%

A Basis for Formal Robustness Checking

Fey

Drechsler

2008

9th International Symposium on Quality Electronic Design (Isqed 2008)

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“…Various methods have been proposed based on symbolic methods using Binary Decision Diagrams (BDDs) [3]- [6] or Boolean Satisfiability (SAT) [7]- [9]. The approaches of [6], [8], [9] are most tightly related to our approach.…”

Section: Introductionmentioning

confidence: 99%

A better-than-worst-case robustness measure

Frehse

Fey

Drechsler

2010

13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems

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Abstract-In presence of increasing soft error rates due to shrinking feature sizes, design tools are required to analyze fault tolerance and robustness of circuits.Here, we propose a new measure that identifies hot-spots in the design. On the one hand the measure is more accurate than a "worst-case analysis" that ignores excitation probabilities. On the other hand the computation of the new measure is more efficient than a "probabilistic analysis" that considers excitation probabilities at the cost of a higher computational complexity. Both of these extremes can be embedded in the new measure. Experimental results on circuits with protection against soft errors show that the new measure can be calculated effectively.

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Evaluating Coverage of Error Detection Logic for Soft Errors using Formal Methods

Cited by 41 publications

References 13 publications

SymPLFIED: Symbolic Program-Level Fault Injection and Error Detection Framework

SymPLFIED: Symbolic Program-Level Fault Injection and Error Detection Framework

A Basis for Formal Robustness Checking

A better-than-worst-case robustness measure

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