Evaluating fault-tolerance of redundant FPGA structures using Boolean difference calculus

Anwer, Jahanzeb; Platzner, Marco

doi:10.1016/j.micpro.2017.06.002

Cited by 4 publications

(3 citation statements)

References 11 publications

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“…In fact, output bits that were deemed essential to a system were given greater protection priorities, which lowered the likelihood of catastrophic mistakes. The researcher selected the boolean difference error calculus (BDEC) method that was previously suggested in the literature and expanded it in two ways: first, to account for the impact of reliability-enhancement strategies like redundancy, and second, to encompass sequential circuit parts [12]. Dug et al [13] constructed and examined two techniques for creating fault-tolerant pipelined sequential and combinational circuits on a FPGA board.…”

Section: Previous Workmentioning

confidence: 99%

Design and analysis of fault-tolerant sequential logic circuits for safety-critical applications

Khairullah,

Qassabbashi,

Kareem

2024

Bulletin EEI

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Safety-critical systems used in applications that demand high levels of dependability, efficiency, and fault-tolerance often use sequential logic circuits in its design and implementation. The safety-critical digital system typically uses latches, flip-flops, and other memory elements, which are prone to the effects of natural faults and single event upsets (SEUs) caused by radiation-induced effects. The faults can lead to subsystem failures due to the continuous advancement in the realization of the small size transistor. To design a reliable digital-based system, it is essential to develop new fault-tolerance approaches that are integrated into the design of sequential logic circuits. This work proposes a novel fault-tolerant approach based on the redundancy of sequential logic circuit, which consists of a variety of design components, D flip-flop storage elements linked to a fault injection unit, a duplicate modular redundancy, and data monitoring units with a switching circuit. The experimental simulation results using a five-state Markov chain analysis model prove that the proposed fault-tolerant system can achieve 0.99999998 for reliability of the fault detection coverage (C) which equal to 0.99999. Finally, we believe that using this new approach of fault-tolerance and redundancy would improve the dependability and reliability of next generation safety-critical applications.

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Section: Previous Workmentioning

confidence: 99%

Design and analysis of fault-tolerant sequential logic circuits for safety-critical applications

Khairullah,

Qassabbashi,

Kareem

2024

Bulletin EEI

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“…(i) e mathematical models of these schemes are mature and have been analyzed in the literature [40,41] (ii) e probabilistic schemes are able to comprehend very small differences in reliability among slightly different redundant structures Among the probabilistic computational reliability schemes, we decided to use the Boolean Difference Error Calculator (BDEC) method based on the analysis and merits/demerits of various computation schemes explained in our previous work [40][41][42]. e basic BDEC model was, however, limited as it did not cover sequential circuits and could not deal with redundant circuit structures.…”

Section: Replication Via the Banl Tmr Toolmentioning

confidence: 99%

“…e experimental data used to support the findings of this study are included within the articleas well as in authors' previous research works [40][41][42][48][49][50].…”

Section: Data Availabilitymentioning

confidence: 99%

Dynamic Reliability Management for FPGA-Based Systems

Anwer

Meisner

Platzner

2020

International Journal of Reconfigurable Computing

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Radiation tolerance in FPGAs is an important field of research particularly for reliable computation in electronics used in aerospace and satellite missions. The motivation behind this research is the degradation of reliability in FPGA hardware due to single-event effects caused by radiation particles. Redundancy is a commonly used technique to enhance the fault-tolerance capability of radiation-sensitive applications. However, redundancy comes with an overhead in terms of excessive area consumption, latency, and power dissipation. Moreover, the redundant circuit implementations vary in structure and resource usage with the redundancy insertion algorithms as well as number of used redundant stages. The radiation environment varies during the operation time span of the mission depending on the orbit and space weather conditions. Therefore, the overheads due to redundancy should also be optimized at run-time with respect to the current radiation level. In this paper, we propose a technique called Dynamic Reliability Management (DRM) that utilizes the radiation data, interprets it, selects a suitable redundancy level, and performs the run-time reconfiguration, thus varying the reliability levels of the target computation modules. DRM is composed of two parts. The design-time tool flow of DRM generates a library of various redundant implementations of the circuit with different magnitudes of performance factors. The run-time tool flow, while utilizing the radiation/error-rate data, selects a required redundancy level and reconfigures the computation module with the corresponding redundant implementation. Both parts of DRM have been verified by experimentation on various benchmarks. The most significant finding we have from this experimentation is that the performance can be scaled multiple times by using partial reconfiguration feature of DRM, e.g., 7.7 and 3.7 times better performance results obtained for our data sorter and matrix multiplier case studies compared with static reliability management techniques. Therefore, DRM allows for maintaining a suitable trade-off between computation reliability and performance overhead during run-time of an application.

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Planned Obsolescence Using Nanotechnology for Protection Against Artificial Intelligence

Martins

Barone

2017

Communications in Computer and Information Science

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Evaluating fault-tolerance of redundant FPGA structures using Boolean difference calculus

Cited by 4 publications

References 11 publications

Design and analysis of fault-tolerant sequential logic circuits for safety-critical applications

Design and analysis of fault-tolerant sequential logic circuits for safety-critical applications

Dynamic Reliability Management for FPGA-Based Systems

Planned Obsolescence Using Nanotechnology for Protection Against Artificial Intelligence

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