Evaluating persistent memory range indexes

Lersch, Lucas; Hao, Xiangpeng; Oukid, Ismail; Wang, Tianzheng; Willhalm, Thomas

doi:10.14778/3372716.3372728

Cited by 76 publications

(36 citation statements)

References 24 publications

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“…We have experimented with varying block sizes as well as degrees of parallelism (i.e., threads and I/O depth) and report the best throughput. The measurements are largely in accordance with the specifications and other reports [9,11,18,32,38]. One anomaly, however, is the sequential write bandwidth for DRAM, which should be closer to the read speed.…”

Section: Persistent Memorysupporting

confidence: 88%

“…They propose a persistent linked list of leaf nodes while keeping the inner nodes in DRAM, which are rebuilt upon recovery. Evaluations on real hardware have already shown that this division is definitely practical for hiding PMem's higher latency and achieving DRAM-like performance [18]. With the LB + -Tree [22] the authors refine the concept for Intel's DCPMMs by utilizing multi-256-byte nodes and limiting the number of PMem line writes.…”

Section: Multi-level Data Structuresmentioning

confidence: 99%

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Designing an Event Store for a Modern Three-layer Storage Hierarchy

et al. 2020

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Event stores face the difficult challenge of continuously ingesting massive temporal data streams while satisfying demanding query and recovery requirements. Many of today’s systems deal with multiple hardware-based trade-offs. For instance, long-term storage solutions balance keeping data in cheap secondary media (SSDs, HDDs) and performance-oriented main-memory caches. As an alternative, in-memory systems focus on performance, while sacrificing monetary costs, and, to some degree, recovery guarantees. The advent of persistent memory (PMem) led to a multitude of novel research proposals aiming to alleviate those trade-offs in various fields. So far, however, there is no proposal for a PMem-powered specialized event store. Based on ChronicleDB, we will present several complementary approaches for a three-layer architecture featuring main memory, PMem, and secondary storage. We enhance some of ChronicleDB’s components with PMem for better insertion and query performance as well as better recovery guarantees. At the same time, the three-layer architecture aims to keep the overall dollar cost of a system low. The limitations and opportunities of a PMem-enhanced event store serve as important groundwork for comprehensive system design exploiting a modern storage hierarchy.

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Section: Persistent Memorysupporting

confidence: 88%

Section: Multi-level Data Structuresmentioning

confidence: 99%

Designing an Event Store for a Modern Three-layer Storage Hierarchy

et al. 2020

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“…We observe that Px86's asynchronous explicit persist instructions lie in sharp contrast with a variety of previous work and developers' guides, ranging from theory to practice, that assumed, sometimes implicitly, łsynchronousž explicit persist instructions that allow the programmer to assert that certain write must have persisted at certain program points (e.g., [Arulraj et al 2018;Chen and Jin 2015;David et al 2018;Friedman et al 2020Friedman et al , 2018Gogte et al 2018;Izraelevitz et al 2016b;Kolli et al 2017Kolli et al , 2016Lersch et al 2019;Liu et al 2020;Oukid et al 2016;Scargall 2020;Venkataraman et al 2011;Yang et al 2015;Zuriel et al 2019]). For example, Izraelevitz et al [2016b]'s psync instruction blocks until all previous explicit persist institutions łhave actually reached persistent memoryž, but such instruction cannot be implemented in Px86.…”

Section: Introductioncontrasting

confidence: 69%

Taming x86-TSO persistency

Khyzha

Lahav

2021

Proc. ACM Program. Lang.

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We study the formal semantics of non-volatile memory in the x86-TSO architecture. We show that while the explicit persist operations in the recent model of Raad et al. from POPL'20 only enforce order between writes to the non-volatile memory, it is equivalent, in terms of reachable states, to a model whose explicit persist operations mandate that prior writes are actually written to the non-volatile memory. The latter provides a novel model that is much closer to common developers' understanding of persistency semantics. We further introduce a simpler and stronger sequentially consistent persistency model, develop a sound mapping from this model to x86, and establish a data-race-freedom guarantee providing programmers with a safe programming discipline. Our operational models are accompanied with equivalent declarative formulations, which facilitate our formal arguments, and may prove useful for program verification under x86 persistency.

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“…Still, a combination of both seems promising. Since former experiments work on emulated PMem, in [22], the authors re-evaluated the B + -Tree variants on real hardware. In [10,11], the underlying primitives of these trees are also analyzed on real PMem.…”

Section: Related Workmentioning

confidence: 99%

Selective caching: a persistent memory approach for multi-dimensional index structures

Jibril

Götze

Broneske

et al. 2021

Distrib Parallel Databases

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After the introduction of Persistent Memory in the form of Intel’s Optane DC Persistent Memory on the market in 2019, it has found its way into manifold applications and systems. As Google and other cloud infrastructure providers are starting to incorporate Persistent Memory into their portfolio, it is only logical that cloud applications have to exploit its inherent properties. Persistent Memory can serve as a DRAM substitute, but guarantees persistence at the cost of compromised read/write performance compared to standard DRAM. These properties particularly affect the performance of index structures, since they are subject to frequent updates and queries. However, adapting each and every index structure to exploit the properties of Persistent Memory is tedious. Hence, we require a general technique that hides this access gap, e.g., by using DRAM caching strategies. To exploit Persistent Memory properties for analytical index structures, we propose selective caching. It is based on a mixture of dynamic and static caching of tree nodes in DRAM to reach near-DRAM access speeds for index structures. In this paper, we evaluate selective caching on the OLAP-optimized main-memory index structure Elf, because its memory layout allows for an easy caching. Our experiments show that if configured well, selective caching with a suitable replacement strategy can keep pace with pure DRAM storage of Elf while guaranteeing persistence. These results are also reflected when selective caching is used for parallel workloads.

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Evaluating persistent memory range indexes

Cited by 76 publications

References 24 publications

Designing an Event Store for a Modern Three-layer Storage Hierarchy

Designing an Event Store for a Modern Three-layer Storage Hierarchy

Taming x86-TSO persistency

Selective caching: a persistent memory approach for multi-dimensional index structures

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