Evaluating the Impact of Ionizing Particles on FinFET -based SRAMs with Weak Resistive Defects

Abstract

Fin Field-Effect Transistor (FinFET) technology enables the continuous downscaling of Integrated Circuits (ICs), using the Complementary Metal-Oxide Semiconductor (CMOS) technology in accordance with the More Moore domain. Despite demonstrating improvements on short channel effect and overcoming the growing leakage problem of planar CMOS technology, the continuity of feature size miniaturization allowed by FinFETs tends to increase sensitivity to Single Event Upsets (SEUs) caused by ionizing particles, especially in blocks with higher transistor densities as Static Random-Access Memories (SRAMs). Variation during the manufacturing process has introduced different types of defects that directly affect the SRAM's reliability, such as weak resistive defects. As some of these defects may cause dynamic faults, which require more than one consecutive operation to sensitize the fault at the logic level, traditional test approaches may fail to detect them and test escapes can occur. These undetected faults associated with weak resistive defects may affect the FinFET-based SRAM reliability during the lifetime. In this context, this paper proposes to investigate the impact of ionizing particles on the reliability of FinFET-based SRAMs in the presence of weak resistive defects. Firstly, a TCAD model of a FinFET-based SRAM cell is proposed in order to allow the evaluation of the ionizing particle's impact. Then, SPICE simulations are performed considering the current pulse parameters obtained with TCAD. In this step, weak resistive defects are injected into the FinFETbased SRAM cell. Results show that weak defects may have either a positive or negative influence on the cell reliability against SEUs caused by ionizing particles.

Evaluation of Single Event Upset Susceptibility of FinFET-based SRAMs with Weak Resistive Defects

“…Hence, the main contributions of this paper are: 1) obtain, by physical simulation, the minimum value of Linear Energy Transfer (LET) of an incident particle that results in a bit-flip ( LET th , or threshold LET) for FinFET SRAM cells designed in a technology equivalent to a 14 nm node; 2) propose a SPICE model for the obtained current curves; 3) investigate the impact of SEUs on the reliability of FinFET-based SRAMs with weak resistive defects. Note that the first step towards these goals was presented in [9]. Thus, this publication extends the explanations regarding the proposed simulation flow during experiments, improves the development of the transistor's electrical characteristics, and enhances the SRAM cell's analysis with respect to regions far from the critical node.…”