Evaluating the Impact of Process Variation on RRAMs

Brum, E.; Fieback, Moritz; Copetti, T.; Jia-yi, HE; Hamdioui, Said; Vargas, F.; Poehls, L. M. Bolzani

doi:10.1109/lats53581.2021.9651789

Cited by 9 publications

(3 citation statements)

References 16 publications

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“…To resume, a small variation in the N disk min value makes the device not able to switch to HRS. A complete study about the impact of electrical parameters variation on the memristive device behavior is published in [27]. Moreover, REF0 was set to 1.3 V and REF1 to 0.70 V. Fig.…”

Section: Obtained Results and Discussionmentioning

confidence: 99%

“…Finally, the adopted voltage for performing a write '1' operation, or in other words a SET operation, is equal to 1.6 V, which is the nominal voltage adopted in the entire circuit. The RESET operation (write '0') is performed by applying a voltage of -1.7 V, and a read operation is performed applying a small voltage of 0.16 V. Note that one version of this block was presented in the previous work in [27], with the difference that the SL is connected via the rows instead of columns, because in the original circuit is not possible to read the memristor row by through the SL node. Regarding the proposed strategy's implementation granularity, an ON CS per RRAM column was introduced and connected using SL.…”

Section: Methodsmentioning

confidence: 99%

“…The ON CS is activated by the Read signal and has two output signals, Data Out and ON CS Out. It is important to mention that the original RRAM block's Sense Amplifier was modified since the ON CS requires a special circuitry during a read operations [27]. During a read operation, the BL-driver applies the V read on the selected RRAM cell and SL-driver set Gnd to SL.…”

Section: Methodsmentioning

confidence: 99%

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Exploring an On-Chip Sensor to Detect Unique Faults in RRAMs

Copetti

Nilovic

Fieback

et al. 2022

2022 IEEE 23rd Latin American Test Symposium (LATS)

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Memristive devices have become promising candidates to complement and/or replace the CMOS technology, due to their CMOS manufacturing process compatibility, zero standby power consumption, high scalability, as well as their capability to implement high-density memories and new computing paradigms. Despite these advantages, memristive devices are also susceptible to manufacturing defects that may cause different faulty behaviors not observed in CMOS technology, significantly increasing the manufacturing test complexity. This work proposes a Design-for-Testability (DfT) strategy based on the introduction of a on-chip sensor that measures the current consumption of Resistive Random Access Memories (RRAMs) cells to provide the detection of unique faults. The new On-Chip Sensor (ON CS) was validated using a case study 3x3 RRAM cell array with peripheral circuitry implemented based on a 130 nm Predictive Technology Model (PTM) library. Experimental results show that the proposed DfT strategy is able to detect not only traditional faults, but also unique faults that can affect RRAM cells. Finally, this paper proposes an DfT strategy that can detect unique faults with an unique operation and can be used during the normal operation of a RRAM.

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Section: Obtained Results and Discussionmentioning

confidence: 99%

Section: Methodsmentioning

confidence: 99%

Section: Methodsmentioning

confidence: 99%

See 1 more Smart Citation

Exploring an On-Chip Sensor to Detect Unique Faults in RRAMs

Copetti

Nilovic

Fieback

et al. 2022

2022 IEEE 23rd Latin American Test Symposium (LATS)

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A DfT Strategy for Guaranteeing ReRAM’s Quality after Manufacturing

Copetti,

Fieback,

Gemmeke

et al. 2024

J Electron Test

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Memristive devices have become promising candidates to complement the CMOS technology, due to their CMOS manufacturing process compatibility, zero standby power consumption, high scalability, as well as their capability to implement high-density memories and new computing paradigms. Despite these advantages, memristive devices are susceptible to manufacturing defects that may cause faulty behaviors not observed in CMOS technology, significantly increasing the challenge of testing these novel devices after manufacturing. This work proposes an optimized Design-for-Testability (DfT) strategy based on the introduction of a DfT circuitry that measures the current consumption of Resistive Random Access Memory (ReRAM) cells to detect not only traditional but also unique faults. The new DfT circuitry was validated using a case study composed of a 3x3 word-based ReRAM with peripheral circuitry implemented based on a 130 nm Predictive Technology Model (PTM) library. The obtained results demonstrate the fault detection capability of the proposed strategy with respect to traditional and unique faults. In addition, this paper evaluates the impact related to the DfT circuitry’s introduced overheads as well as the impact of process variation on the resolution of the proposed DfT circuitry.

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Embedded Tutorial - RRAMs: How to Guarantee Their Quality Test after Manufacturing?

Poehls

2023

2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)

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Evaluating the Impact of Process Variation on RRAMs

Cited by 9 publications

References 16 publications

Exploring an On-Chip Sensor to Detect Unique Faults in RRAMs

Exploring an On-Chip Sensor to Detect Unique Faults in RRAMs

A DfT Strategy for Guaranteeing ReRAM’s Quality after Manufacturing

Embedded Tutorial - RRAMs: How to Guarantee Their Quality Test after Manufacturing?

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