Evaluating the Impact of Temperature on Dynamic Fault Behaviour of FinFET-Based SRAMs with Resistive Defects

Medeiros, Guilherme Cardoso; Brum, E.; Poehls, Leticia Bolzani; Copetti, T.; Balen, Tiago R.

doi:10.1007/s10836-019-05784-1

Cited by 4 publications

(6 citation statements)

References 22 publications

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“…Moreover, the nominal power supply adopted is of 0.95 V for the CMOS block and of 0.9 V for the FinFET memory. Both memory blocks were connected to other functional blocks, such as sense amplifier, decoders and output latch, which are based on traditional SRAM designs [25]. The clock signal was set to operate with a frequency of 1GHz.…”

Section: Methodsmentioning

confidence: 99%

“…Furthermore, the paper shows that static coupling faults are typical for both FinFET-and planar-based SRAMs. In [25], the impact of temperature on the dynamic fault behavior has been analyzed showing how test procedures for FinFET memories can benefit from properly adjusting the operating temperature to detect resistive defects and avoid test escapes.…”

Section: Introductionmentioning

confidence: 99%

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Comparing the Impact of Power Supply Voltage on CMOS- and FinFET-Based SRAMs in the Presence of Resistive Defects

et al. 2020

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CMOS technology scaling has reached its limit at the 22 nm technology node due to several factors including Process Variations (PV), increased leakage current, Random Dopant Fluctuation (RDF), and mainly the Short-Channel Effect (SCE). In order to continue the miniaturization process via technology down-scaling while preserving system reliability and performance, Fin Field-Effect Transistors (FinFETs) arise as an alternative to CMOS transistors. In parallel, Static Random-Access Memories (SRAMs) increasingly occupy great part of Systems-on-Chips' (SoCs) silicon area, making their reliability an important issue. SRAMs are designed to reach densities at the limit of the manufacturing process, making this component susceptible to manufacturing defects, including the resistive ones. Such defects may cause dynamic faults during the circuits' lifetime, an important cause of test escape. Thus, the identification of the proper faulty behavior taking different operating conditions into account is considered crucial to guarantee the development of more suitable test methodologies. In this context, a comparison between the behavior of a 22 nm CMOS-based and a 20 nm FinFET-based SRAM in the presence of resistive defects is carried out considering different power supply voltages. In more detail, the behavior of defective cells operating under different power supply voltages has been investigated performing SPICE simulations. Results show that the power supply voltage plays an important role in the faulty behavior of both CMOS-and FinFET-based SRAM cells in the presence of resistive defects but demonstrate to be more expressive when considering the FinFET-based memories. Studying different operating temperatures, the results show an expressively higher occurrence of dynamic faults in FinFET-based SRAMs when compared to CMOS technology.

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Section: Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Comparing the Impact of Power Supply Voltage on CMOS- and FinFET-Based SRAMs in the Presence of Resistive Defects

et al. 2020

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“…[11] investigated the parameter variation impact on FinFET-specific fault module and coverage. [3][12][13] [14] studied the effect of resistive defects on the behavior of FinFET memory and obtained the corresponding functional fault model through experiments. This paper mainly studies the functional fault model of FinFET memory, which included static single-cell FFMs, static double-cell FFMs, dynamic single-cell FFMs, dynamic double-cell FFMs, etc.…”

Section: Finfet Functional Fault Modelmentioning

confidence: 99%

“…However, FinFET memories may also suffer from functional faults caused by multiple sensitization operations. It is found that there are two or more read operations in dRDF and dDRDF when FinFET memory is affected by resistive defects [3][13] [14]. The effect of temperature on the occurrence of dynamic memory faults and the number of consecutive operations necessary to sensitize faults at the logic level are investigated in [14].…”

Section: Finfet Functional Fault Modelmentioning

confidence: 99%

“…It is found that there are two or more read operations in dRDF and dDRDF when FinFET memory is affected by resistive defects [3][13] [14]. The effect of temperature on the occurrence of dynamic memory faults and the number of consecutive operations necessary to sensitize faults at the logic level are investigated in [14]. Figure 1 presents the frequency of dynamic fault of FinFET memory with resistive defects at nominal temperature (24℃-32℃).…”

Section: Finfet Functional Fault Modelmentioning

confidence: 99%

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A new march test for FinFET memory functional fault detection

Wang

Huang

Cai

et al. 2023

2022 Workshop on Electronics Communication Engineering

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FinFET (Fin Field-Effect Transistor) technology is widely used in advanced transistor manufacturing process due to its lower leakage current, smaller short-channel effect, and lower power consumption. However, this special physical structure is very susceptible to manufacturing defects, which makes the FinFET memory prone to functional faults. Therefore, an efficient fault detection method is very important for the defect detection of FinFET memory. A detection algorithm called March FRD for FinFET memory faults is proposed in this paper. This paper summarizes the FinFET functional fault model, analyzes the corresponding coverage conditions, and verifies the correctness of the algorithm. March FRD performs well in detecting resistance dynamic faults, and its total fault coverage reaches 91.7%, which is significantly better than other existing March tests.

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Tightening the Mesh Size of the Cell-Aware ATPG Net for Catching All Detectable Weakest Faults

Gao

Malagi

et al. 2020

2020 IEEE European Test Symposium (ETS)

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Evaluating the Impact of Temperature on Dynamic Fault Behaviour of FinFET-Based SRAMs with Resistive Defects

Cited by 4 publications

References 22 publications

Comparing the Impact of Power Supply Voltage on CMOS- and FinFET-Based SRAMs in the Presence of Resistive Defects

Comparing the Impact of Power Supply Voltage on CMOS- and FinFET-Based SRAMs in the Presence of Resistive Defects

A new march test for FinFET memory functional fault detection

Tightening the Mesh Size of the Cell-Aware ATPG Net for Catching All Detectable Weakest Faults

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