Evaluating the performance of a configurable, extensible VLIW processor in FFT execution

Stevens, David; Glynn, N.; Galiatsatos, P.; Chouliaras, V.A.; Reisis, D.

doi:10.1109/icecs.2009.5410773

Cited by 4 publications

(1 citation statement)

References 8 publications

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“…2 and consists of a standard host processor (Leon3 for standard-cell technologies and the Xilinx Microblaze for FPGA targets) and a number of default peripherals. A key component of the flow is the multi-core VLIW engine [16,17] (Figs. 2b and 2c) which forms the first-level accelerator.…”

Section: System Synthesis and Exploration Phasementioning

confidence: 99%

VThreads: A novel VLIW chip multiprocessor with hardware-assisted PThreads

Chouliaras

Stevens

Dwyer

2016

Microprocessors and Microsystems

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performance increase on synthetic benchmarks, x5 on a parallel Mandelbrot implementation, 66% better on a threaded JPEG implementation, 79% better on an edge-detection benchmark and~13% improvement on DES compared to the Leon3MP CMP. In the range of 2 to 8 cores VThreads demonstrates a post-route (statistical) power reduction between 65% to 57% at an area increase of 1.2%-10% for 1-8 cores, compared to a similarly-configured Leon3MP CMP. This combination of micro-architectural features, scalability, extensibility, hardware support for low-latency PThreads, power efficiency and area make the processor an attractive proposition for low-power, deeply-embedded applications requiring minimum OS support.

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Section: System Synthesis and Exploration Phasementioning

confidence: 99%

VThreads: A novel VLIW chip multiprocessor with hardware-assisted PThreads

Chouliaras

Stevens

Dwyer

2016

Microprocessors and Microsystems

Self Cite

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Notice of Violation of IEEE Publication Principles - Super-scale architecture enhancement of LEON3 core for DSP application

Mehta

Darji

Ram

et al. 2015

2015 19th International Symposium on VLSI Design and Test

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Embedded UML design flow to the configurable LE1 MultiCore VLIW processor

Milward

Stevens

Chouliaras

2012

7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)

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This paper presents a tool-supported UML design flow (ENOSYS flow) for designing and implementing embedded systems through the seamless integration of high-level system specification, hardware synthesis, embedded soft VLIW multi-core processors and design space exploration. Using the proposed design flow, investigations into the trade-offs between various multi-core processor parameters such as the issue width of the VLIW cores and the number of processor cores are performed. Many design permutations of the multiprocessor are automatically synthesised for a Virtex6 FPGA board and design characteristics extracted. An example DES UML model was taken through the developed design flow and executed on a retargetable multi-core simulator to assess performance figures. The resulting binaries are verified by running on the generated bit streams downloaded on the target FPGA board.

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Evaluating the performance of a configurable, extensible VLIW processor in FFT execution

Cited by 4 publications

References 8 publications

VThreads: A novel VLIW chip multiprocessor with hardware-assisted PThreads

VThreads: A novel VLIW chip multiprocessor with hardware-assisted PThreads

Notice of Violation of IEEE Publication Principles - Super-scale architecture enhancement of LEON3 core for DSP application

Embedded UML design flow to the configurable LE1 MultiCore VLIW processor

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