Evaluation and Comparison of 3.0 nm Gate-Stack Dielectrics for Tenth-Micron Technology NMOSFETs

Abstract

As device dimensions continue to scale down into the deep submicrometer regime, there is an increasing challenge for fabricating robust gate dielectrics with low susceptibility to process-induced device degradation and a continuous motivation for the exploration of new options for thin gate dielectrics. This work assesses a variety of gate stack processing techniques as alternatives to conventionally furnace grown gate oxides in the context of a tenth-micron technology, which features LOCOS isolated, two-implant channel, NMOS transistors fabricated with a 3.0 nm thick gate dielectric, 0.15 μm thick polysilicon gate, implanted extension- and contact-junctions of 20 and 50 nm deep, respectively, and effective channel lengths down to 0.12 μm, operating at 1.2 volts. The alternative deposition and oxidation techniques include furnace oxynitride formation, rapid-thermal oxidation (RTO), rapid-thermal chemical vapor deposition (RTCVD) and plasma-assisted chemical vapor deposition (RPECVD). Compared to the 0.25- and 0.18-μm technological nodes, the thermal budgets associated with gate oxide formation are dramatically lower and their impact on channel dopant redistribution is not as strong as in previous technologies. Negligible polysilicon depletion effects were observed in the fabricated devices (Cinv/Cox = 97%). Drive currents and threshold voltage control comparable to furnace oxides were achieved by alternative gate-stack processing techniques.