Device simulations and response surface analysis have been used to quantify the trade-offs and issues encountered in designing ultrashallow junctions for the 250-50 nm generations of complimentary metal-oxide-semiconductor ultralarge scale integration technology. The design of contacting and extension junctions is performed to optimize short channel effects, performance, and reliability, while meeting the National Technology Roadmap for Semiconductors off-state leakage specifications. A maxima in saturated drive current is observed for an intermediate extension junction depth ͑ϳ20 nm for 100 nm technology͒: shallower junctions lead to higher series resistance, and deeper junctions result in more severe short channel effects. The gate-to-junction overlap required to preserve drive current was seen to depend on junction abruptness. For a perfectly abrupt junction, it is not necessary for the gate to overlap the junction. Performance depends on many parameters, including: overlap of gate to extension junction, junction capacitance, and parasitic series resistance, which depends on the doping gradient at the junction ͑spreading resistance͒, the extension series resistance, and the contact resistance. Extraction of these parameters using I -V or C -V measurements can potentially lead to erroneous conclusions about lateral junction excursion and abruptness.

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As device dimensions continue to scale down into the deep submicrometer regime, there is an increasing challenge for fabricating robust gate dielectrics with low susceptibility to process-induced device degradation and a continuous motivation for the exploration of new options for thin gate dielectrics. This work assesses a variety of gate stack processing techniques as alternatives to conventionally furnace grown gate oxides in the context of a tenth-micron technology, which features LOCOS isolated, two-implant channel, NMOS transistors fabricated with a 3.0 nm thick gate dielectric, 0.15 μm thick polysilicon gate, implanted extension- and contact-junctions of 20 and 50 nm deep, respectively, and effective channel lengths down to 0.12 μm, operating at 1.2 volts. The alternative deposition and oxidation techniques include furnace oxynitride formation, rapid-thermal oxidation (RTO), rapid-thermal chemical vapor deposition (RTCVD) and plasma-assisted chemical vapor deposition (RPECVD). Compared to the 0.25- and 0.18-μm technological nodes, the thermal budgets associated with gate oxide formation are dramatically lower and their impact on channel dopant redistribution is not as strong as in previous technologies. Negligible polysilicon depletion effects were observed in the fabricated devices (Cinv/Cox = 97%). Drive currents and threshold voltage control comparable to furnace oxides were achieved by alternative gate-stack processing techniques.