Vertically scaled MOSFET gate stacks and junctions: How far are we likely to go?

Osburn, C. M.; Kim, I.; Han, Suyong; De, Indranil; Yee, K. F.; Gannavaram, S.; Lee, S. J.; Lee, C.-H.; Luo, Zhijiong; Zhu, Wenjuan; Hauser, John R.; Kwong, Dim‐Lee; Lucovsky, G.; P., T.; Öztürk, Mehmet C.

doi:10.1147/rd.462.0299

Cited by 32 publications

(12 citation statements)

References 63 publications

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“…HfO 2 is one of the most promising candidates for dielectric layers in complementary metal±oxide semiconductor devices, [1] owing to its high dielectric constant (12±28). [2,3] In addition, HfO 2 films have been investigated for applications in optics.…”

Section: Introductionmentioning

confidence: 99%

Atomic Layer Deposition of Hafnium Dioxide Films from Hafnium Hydroxylamide and Water

Kukli

Ritala

Leskelä

et al. 2004

Chemical Vapor Deposition

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HfO 2 films were grown by atomic layer deposition (ALD) from a new liquid precursor, Hf(ONEt 2 ) 4 and H 2 O, at temperatures between 250 C and 350 C on borosilicate glass and Si(100) substrates. The highest growth rate was achieved at 300 C, whereas the growth was essentially slower at 250 C and ceased at 350 C. The films possessed an O:Hf ratio of 2.15 ± 0.12, as determined by ion beam analysis. The films were weakly crystallized, showing X-ray diffraction (XRD) peaks characteristic of monoclinic phase. The refractive index of the films varied between 1.93 and 1.96. The effective permittivities of the dielectric layers in Al/HfO 2 /n-Si(100) capacitor structures were close to 10.

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Section: Introductionmentioning

confidence: 99%

Atomic Layer Deposition of Hafnium Dioxide Films from Hafnium Hydroxylamide and Water

Kukli

Ritala

Leskelä

et al. 2004

Chemical Vapor Deposition

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“…But the density of IC is increased, such as; the density of DRAM is more than 1 G bits per chip. Same as the scale down of the channel length, the width of gate, the thickness of gate oxide, and the junction depth of source/drain are also reduced [6][7][8][9][10][11]. All of these reductions will cause decrease in the immunity to prevent the damage from the electrostatic charge.…”

Section: Introductionmentioning

confidence: 99%

Pseudo-Failure Impacts on ESD Robustness in Integrated Circuits I/O Ports by the Parasitic Capacitance

Chen¹,

Chen²

2014

TOEEJ

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Semiconductor components are commonly electrostatic discharge (ESD) sensitive. The ESD event would usually cause a harm or destruction of the devices. Due to the requirement of circuits' reliability, the test for ESD robustness is necessary for almost all the product of integrated circuits. But during the test of ESD zapping, the test pin may temporary store ESD zapping charges. These stored charges will temporary cause shifting of the I-V characteristic curve of the test pin. And, it will seriously influence the ESD test results. Therefore, the electrostatic discharge (ESD) properties of the IC products in terms of the internal parasitic capacitance of the test pin are investigated in this paper. Eventually, it is found if the parasitic capacitance of the test pin is over 10-pf, the ESD test results may be not correct. We find, by suitable adjustment, the delay time between the ESD zapping and the measurement of I-V characteristic curve, a more correct result can be obtained. Therefore, it can correct the mistake made by parasitic capacitance in ICs and have a reliable ESD test result.

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“…The high-K materials that could potentially replace SiO 2 include Ta 2 O 5 , TiO 2 , Y 2 O 3 , CeO 2 , SrTiO 3 , Zr-Sn-Ti-O, Al 2 O 3 , La 2 O 3 , HfO 2 , and ZrO 2 . Related research has been rapidly increasing [1][2][3][4][5][6].…”

Section: Introductionmentioning

confidence: 99%

“…According to Ref [1],. the relative dielectric constants of HfO 2 and ZrO 2 range from 16 to 30 and from 12 to 16, respectively.…”

mentioning

confidence: 99%

Effects of Dielectric Constant Mismatch on Capacitance-voltage Curve

Mao¹

2009

IETE J Res

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This paper investigates the effects of a dielectric-constant mismatch between gate dielectric and silicon substrate on the capacitance-voltage curve of high-K MOS structures, numerically, via fully self-consistent solutions of Schrödinger and Poisson equations. Results demonstrate that the capacitance-voltage curve of a high-K MOS structure compared to that of SiO 2 MOS structure with the same equivalent oxide thickness shifts to lower gate voltage with increasing dielectric constant of the gate dielectric, thickness of gate dielectric, and acceptor density in silicon substrate. The results also demonstrate that a higher dielectric thickness, thicker gate dielectric, and higher acceptor density for a high-K MOS structure lead to a larger increase in capacitance compared to SiO 2 MOS structure with the same equivalent oxide thickness.

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Vertically scaled MOSFET gate stacks and junctions: How far are we likely to go?

Cited by 32 publications

References 63 publications

Atomic Layer Deposition of Hafnium Dioxide Films from Hafnium Hydroxylamide and Water

Atomic Layer Deposition of Hafnium Dioxide Films from Hafnium Hydroxylamide and Water

Pseudo-Failure Impacts on ESD Robustness in Integrated Circuits I/O Ports by the Parasitic Capacitance

Effects of Dielectric Constant Mismatch on Capacitance-voltage Curve

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