Evaluation of a low-power reconfigurable DSP architecture

Abnous, A.; Seno, K.; Ichikawa, Yuji; Wan, M.; Rabaey, Jan M.

doi:10.1007/3-540-64359-1_673

Cited by 33 publications

(12 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…We experimented with a systems-architecture that accommodated the required functionality, within the energy limitation constrains of a small battery-powered device. This systems-architecture has some similarities with the Desk Area Network in Cambridge [5] and the Pleiades project in Berkeley [1] [2].…”

Section: Reconfigurable Media Streamsmentioning

confidence: 97%

Chameleon — Reconfigurability in Hand-Held Multimedia Computers

Smit¹,

Bos²,

Havinga³

et al. 1999

Handheld and Ubiquitous Computing

View full text Add to dashboard Cite

Abstract. This paper discusses reconfigurability issues in low-power hand-held multimedia systems, with particular emphasis on energy conservation. We claim that a radical new approach has to be taken in order to fulfill the requirements -in terms of processing power and energy consumption -of future mobile applications. A reconfigurable systems-architecture in combination with a QoS driven operating system is introduced that can deal with the inherent dynamics of a mobile system. We present the preliminary results of studies we have done on reconfiguration in hand-held mobile computers: by having reconfigurable media streams, by using reconfigurable processing modules and by migrating functions.

show abstract

Section: Reconfigurable Media Streamsmentioning

confidence: 97%

Chameleon — Reconfigurability in Hand-Held Multimedia Computers

Smit¹,

Bos²,

Havinga³

et al. 1999

Handheld and Ubiquitous Computing

View full text Add to dashboard Cite

show abstract

“…Piperench is one such approach which exploits virtualized hardware, and run-time reconfiguration [13]. Pleiades is a reconfigurable DSP architecture that uses half the power of an Intel StrongARM for FFT calculations [1].…”

Section: Related Workmentioning

confidence: 99%

A low-power accelerator for the SPHINX 3 speech recognition system

Mathew

Davis

Fang

2003

Proceedings of the 2003 International Conference on Compilers, Architecture and Synthesis for Embedded Systems

View full text Add to dashboard Cite

Accurate real-time speech recognition is not currently possible in the mobile embedded space where the need for natural voice interfaces is clearly important. The continuous nature of speech recognition coupled with an inherently large working set creates significant cache interference with other processes. Hence real-time recognition is problematic even on high-performance general-purpose platforms. This paper provides a detailed analysis of CMU's latest speech recognizer (Sphinx 3.2), identifies three distinct processing phases, and quantifies the architectural requirements for each phase. Several optimizations are then described which expose parallelism and drastically reduce the bandwidth and power requirements for real-time recognition. A special-purpose accelerator for the dominant Gaussian probability phase is developed for a 0.25µ CMOS process which is then analyzed and compared with Sphinx's measured energy and performance on a 0.13µ 2.4 GHz Pentium 4 system. The results show an improvement in power consumption by a factor of 29 at equivalent processing throughput. However after normalizing for process, the special-purpose approach has twice the throughput, and consumes 104 times less energy than the general-purpose processor. The energy-delay product is a better comparison metric due to the inherent design trade-offs between energy consumption and performance. The energy-delay product of the special-purpose approach is 196 times better than the Pentium 4. These results provide strong evidence that real-time large vocabulary speech recognition can be done within a power budget commensurate with embedded processing using today's technology.

show abstract

“…With reconfigurable resources, these processors were able to compute with greater efficiency than software alone, having less software overhead due to address generation, branching, and function calls and exploiting more parallelism than is possible with the processor's normal data path. One hybrid processor-RL system called Pleiades [9,10] has specifically targeted ultra-low power, embedded digital signal processing. The approach fuses an ARM core with a combination of reconfigurable logic, reconfigurable data path, and/or reconfigurable data-flow resources.…”

Section: Why a Dsp Hybrid?mentioning

confidence: 99%

Reconfigurable Processors for High-Performance, Embedded Digital Signal Processing

Graham

Nelson

1999

Lecture Notes in Computer Science

View full text Add to dashboard Cite

Abstract. For high-performance, embedded digital signal processing, digital signal processors (DSPs) are very important. Further, they have many features which make their integration with on-chip reconfigurable logic (RL) resources feasible and beneficial. In this paper, we discuss how this integration might be done and the potential area costs and performance benefits of incorporating RL onto a DSP chip. For our proposed architecture, a reconfigurable coprocessor can provide speed-ups ranging from 2-32x with an area cost of about a second DSP core for a set of signal processing applications and kernels.

show abstract

Evaluation of a low-power reconfigurable DSP architecture

Cited by 33 publications

References 3 publications

Chameleon — Reconfigurability in Hand-Held Multimedia Computers

Chameleon — Reconfigurability in Hand-Held Multimedia Computers

A low-power accelerator for the SPHINX 3 speech recognition system

Reconfigurable Processors for High-Performance, Embedded Digital Signal Processing

Contact Info

Product

Resources

About