Reconfigurable Processors for High-Performance, Embedded Digital Signal Processing

Abstract

Abstract. For high-performance, embedded digital signal processing, digital signal processors (DSPs) are very important. Further, they have many features which make their integration with on-chip reconfigurable logic (RL) resources feasible and beneficial. In this paper, we discuss how this integration might be done and the potential area costs and performance benefits of incorporating RL onto a DSP chip. For our proposed architecture, a reconfigurable coprocessor can provide speed-ups ranging from 2-32x with an area cost of about a second DSP core for a set of signal processing applications and kernels.

Improving DSP Performance with a Small Amount of Field Programmable Logic

“…Starting with the PRISC project in Harvard [13] and the work in BYU [3] on integration of DSP and reconfigurable logic and more recently the reconfigurable functional unit idea in the Chimera project in Northwestern University [2], there have been numerous efforts at integrating programmable logic with a processor. The key difference between those efforts and the proposed solution is in two areas (a) we treat DSP + programmable logic integration as a hardware/software co-design problem, hence what we propose is a methodology rather than a specific solution.…”

“…Many researchers have addressed this question in the past and many solutions have been proposed including customized instructions, loops [1], reconfigurable functional units, [2] and co-processor [3,4,5,6,7,8]. However most of the existing approaches do not factor the cost of the programmable logic in their evaluation -they tacitly assume that the die size penalty of adding programmable logic is not important.…”

Description and reconstruction of one-dimensional photonic crystal by digital signal processing theory

“…The optical parameters of the 1DPC are mathematically described from the DSP point of view and thereby become compatible with common MATLAB programs [19] and digital signal processors. [20]…”

The use of a reconfigurable functional cache in a digital signal processor: power and performance

“…It was shown in [2,6,7,8,9] that utilizing part of the level-one cache as a functional unit or other type of reconfigurable hardware can enhance the performance of a GPP. A fine-grained reconfigurable coprocessor for an Analog Device's SHARC DSP was proposed in [10] but it did not measure the power consumption effects of the reconfigurable coprocessor. The research team at the University of California, Berkley, that is working on the Pleiades project have written a plethora of papers [11,12,13,14,15,16,17,18,19,20,21] ontheirproposedreconfigurableDSP.…”

“…An Analog Devices' SHARC floating point DSP was chosen in [10] as the base DSP. The SHARC, which is implemented in 0.6 micron technology has 512KB on-chip memory that is organized as two banks each with an I/0 port so that concurrent memory accesses to each bank do not conflict.…”