Improving DSP Performance with a Small Amount of Field Programmable Logic

Abstract

Abstract. We show a systematic methodology to create DSP + fieldprogrammable logic hybrid architectures by viewing it as a hardware/software codesign problem. This enables an embedded processor architect to evaluate the trade-offs in the increase in die area due to the field programmable logic and the resultant improvement in performance or code size. We demonstrate our methodology with the implementation of a Viterbi decoder. A key result of the paper is that the addition of a field-programmable data alignment unit (FPDAU) between the register-file and the computational blocks provides 15%-22% improvement in the performance of a Viterbi decoder on the state-of-the-art TigerSHARC DSP. The area overhead of the FPDAU is small relative to the DSP die size and does not require any changes to the programming model or the instruction set architecture.

Exploiting data-level parallelism for energy-efficient implementation of LDPC decoders and DCT on an FPGA

“…Second, vector processing requires data alignment to meet the specific requirements of the underlying algorithm. In an FPGA, one can create a custom alignment unit, which will further improve performance and power consumption [Oliver and Akella 2003]. Finally, the reconfigurability of an SRAM-based FPGA allows us to select the optimal degree of vectorization in conjunction with the clock frequency to meet the area and throughput constraints.…”