Exploiting data-level parallelism for energy-efficient implementation of LDPC decoders and DCT on an FPGA

Chen, Xiaoheng; Akella, Venkatesh

doi:10.1145/2068716.2068723

Cited by 6 publications

(4 citation statements)

References 34 publications

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“…In the hardware design of FPGA [4][5][6][7][8], all structure of the LDPC decoder is made up of four modules, which are the information input module, variable node processing units (VNU) module, check node processing units (CNU) module, and the information output module [9][10][11]. Figure.3 is the structure diagram of LDPC decoder in the digital image watermarking system based on the hardware design of FPGA.…”

Section: Design Of Ldpc Decoder Based On Fpgamentioning

confidence: 99%

Design of LDPC Decoder Based On FPGA in Digital Image Watermarking Technology

Wang

Tang

2017

TELKOMNIKA

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Section: Design Of Ldpc Decoder Based On Fpgamentioning

confidence: 99%

Design of LDPC Decoder Based On FPGA in Digital Image Watermarking Technology

Wang

Tang

2017

TELKOMNIKA

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“…This technique is also referred as vector processing [37] (processing a vector of data). In the processing core of Figure 2, all matrix files and the modules of matrix transfer, addition, inversion and multiplication explore bit-level parallelism.…”

Section: Parallelism Techniquesmentioning

confidence: 99%

An Application Specific Instruction Set Processor (ASIP) for Adaptive Filters in Neural Prosthetics

Yao

Zhang

et al. 2015

IEEE/ACM Trans. Comput. Biol. and Bioinf.

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Neural coding is an essential process for neuroprosthetic design, in which adaptive filters have been widely utilized. In a practical application, it is needed to switch between different filters, which could be based on continuous observations or point process, when the neuron models, conditions, or system requirements have changed. As candidates of coding chip for neural prostheses, low-power general purpose processors are not computationally efficient especially for large scale neural population coding. Application specific integrated circuits (ASICs) do not have flexibility to switch between different adaptive filters while the cost for design and fabrication is formidable. In this research work, we explore an application specific instruction set processor (ASIP) for adaptive filters in neural decoding activity. The proposed architecture focuses on efficient computation for the most time-consuming matrix/vector operations among commonly used adaptive filters, being able to provide both flexibility and throughput. Evaluation and implementation results are provided to demonstrate that the proposed ASIP design is area-efficient while being competitive to commercial CPUs in computational performance.

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“…With the advent of field programmable gate array (FPGA), designers can develop a fully reconfigurable hardware architecture dedicated to the control algorithm. In applications where required real‐time capabilities cannot be ensured by software solutions, reconfigurable computers are very useful [8–13]. The cost per implemented function of an FPGA is also very less even though it is more expensive initially.…”

Section: Introductionmentioning

confidence: 99%