Evaluation of branch-prediction methods on traces from commercial applications

Hilgendorf, R.; Heim, G. J.

doi:10.1147/rd.434.0579

Cited by 10 publications

(10 citation statements)

References 18 publications

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“…A BTB miss occurs when an entry for a predicted taken branch is not found in the BTB. Most server workloads used for this study (detailed in Section 4) require up to 16K BTB entries to fully capture all branches in their instruction working sets, while OLTP on Oracle benefits from even 32K entries, corroborating prior work [3,5,18]. The storage capacity requirement of a 32K-entry BTB is around 280KB (Section 4 details the cost).…”

Section: Conventional Instruction-supply Pathsupporting

confidence: 67%

Confluence

Kaynak¹,

Grot

Falsafi³

2015

Proceedings of the 48th International Symposium on Microarchitecture

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Multi-megabyte instruction working sets of server workloads defy the capacities of latency-critical instructionsupply components of a core; the instruction cache (L1-I) and the branch target buffer (BTB). Recent work has proposed dedicated prefetching techniques aimed separately at L1-I and BTB, resulting in high metadata costs and/or only modest performance improvements due to the complex control-flow histories required to effectively fill the two components ahead of the core's fetch stream.This work makes the observation that the metadata for both the L1-I and BTB prefetchers require essentially identical information; the control-flow history. While the L1-I prefetcher necessitates the history at block granularity, the BTB requires knowledge of individual branches inside each block. To eliminate redundant metadata and multiple prefetchers, we introduce Confluence -a frontend design with unified metadata for prefetching into both L1-I and BTB, whose contents are synchronized. Confluence leverages a stream-based prefetcher to proactively fill both components ahead of the core's fetch stream. The prefetcher maintains the control-flow history at block granularity and for each instruction block brought into the L1-I, eagerly inserts the set of branch targets contained in the block into the BTB. Confluence provides 85% of the performance improvement provided by an ideal frontend (with a perfect L1-I and BTB) with 1% area overhead per core, while the highest-performance alternative delivers only 62% of the ideal performance improvement with a per-core area overhead of 8%.

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Section: Conventional Instruction-supply Pathsupporting

confidence: 67%

Confluence

Kaynak¹,

Grot

Falsafi³

2015

Proceedings of the 48th International Symposium on Microarchitecture

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“…At the least, these miss ratios suggest that this workload requires a much larger BTB, and perhaps a different branch prediction method. Hilgendorf and Heim report that BTB miss rates improve for BTBs up to ~16k entries for OLTP workloads [10].…”

Section: How Effective Is Branch Prediction?mentioning

confidence: 99%

Performance characterization of a Quad Pentium Pro SMP using OLTP workloads

Keeton

Patterson

He³

et al. 1998

SIGARCH Comput. Archit. News

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“…The number of bits of the target address to be shifted and the number of previous branches whose history has to be stored is a decision to be made, after considering the effect that various combinations have on the accuracy. Based on traces from commercial applications, Path based scheme is shown to offer the best performance as compared to Pattern and Bimodal schemes [5]. Although Path based scheme has certainly improved the prediction accuracy, we find out that 'Aliasing' effect limits the further performance improvement that can be achieved.…”

Section: Path Based Scheme and Aliasing Effectmentioning

confidence: 87%

“…But is that really helpful? It has been shown that storing history of more than 3-4 branches does not aid in increasing accuracy [5]. In most of the programs, branching decisions are not influenced by the outcomes of branches executed more than 4 basic blocks back.…”

Section: Path Based Scheme and Aliasing Effectmentioning

confidence: 99%

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Alloyed path-pattern scheme for branch prediction

Ramanujam

Ravirala

Lee

Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001

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For more accurate branch prediction, global as well as local histories have been studied and a need f o r hybrid history has emerged. Not only do different parts of a program require different types of histories, but some branches dynamically vary the type of history. To solve this problem, schemes involving dynamic selectors as opposed to static have been proposed. Initially, history represented the directions of previous branches (patternbased). Then came the idea of storing the target addresses of previous branches, thus predicting based on the path ( path-based). The path-and pattern-based schemes do have their drawbacks. This paper studies a potential problem faced by the path-and pattern-based schemes and alleviates it by presenting a new scheme, inwhich the path and pattern histories are alloyed. This scheme is proposed as opposed to having two predictors, path-based and pattern-based, and a selector that dynamically predicts between them. Alloying path and pattern, eliminates the problem of selecting between the two schemes and instead merges the information. It also diminishes the shortcoming of the two schemes and thus acts as a double-edged sword.

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Evaluation of branch-prediction methods on traces from commercial applications

Cited by 10 publications

References 18 publications

Confluence

Confluence

Performance characterization of a Quad Pentium Pro SMP using OLTP workloads

Alloyed path-pattern scheme for branch prediction

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