Evaluation of Cu Contamination at Backside Surface of Thinned Wafer in 3-D Integration by Transient-Capacitance Measurement

Abstract

The influence of Cu contamination at backside surface of a thinned wafer in three-dimensional LSI was electrically evaluated by capacitance-time (C-t) measurement. A MOS capacitor was fabricated using a thinned wafer of 50-μm thickness. The (C-t) curves of the MOS capacitor were severely degraded even after initial annealing at 300 • C for 5 min. It means that Cu atoms at the back surface reach the Si-SiO 2 interface of the front surface, and the generation lifetime is significantly reduced. The quantitative relationship between the generation lifetime and surface concentration of Cu atom was evaluated. The (C-t) measurement is a highly promising method to electrically characterize the influence of Cu contamination on device reliability in fabricated LSI wafers.

3D integration technology and reliability

“…We have evaluated the influences of Cu diffusion into Si substrate by a transient capacitance measurement using an MOS capacitor which is called a capacitance-time (C-t) method [30]. We can deduce the generation lifetime of minor carriers from the Zerbst plot of C-t curve.…”

Recent progress in 3D integration technology

“…Therefore it is more difficult to fabricate Cu-TSV with smaller diameter and larger aspect ratio compared to the via-middle process. On the other hand, we have to be careful for Cu contamination from the Cu-TSV and the backside surface in the via-middle process since the process temperature is higher than that of back-via process [23,24,25]. Mechanical stress induced by Cu-TSVs and metal microbumps, and crystal defects and crystal structure changes produced by thinning the Si substrate are also big concerns in 3D LSIs [26,27].…”

Evaluation of Cu Diffusion From Cu Through-Silicon Via (TSV) in Three-Dimensional LSI by Transient Capacitance Measurement

“…4. The generation lifetime is calculated from Zerbst plot [4]. The Zerbst plot represents the generation of the inversion charge Q inv , which is proportional to the time derivative −d(C ox /C) 2 gives the generation lifetime of the minority carrier.…”

“…For realizing a highly reliable 3-D LSI, it is important to accurately and directly evaluate the influence of Cu diffusion from the Cu TSV on device reliability in a device wafer. We have reported the electrical evaluation method to measure Cu contamination effects at the backside of the thinned device wafer by a transient capacitance measurement, which is called a capacitance-time (C − t) analysis [4]. This method can quantitatively define the generation lifetime of minority carrier in the depletion region, where ionized impurities are compensated by minority carrier generated at deep impurity levels, and the depth of depletion region is reduced [5].…”