Evaluation of data-parallel splitting approaches for H.264 decoding

Seitner, Florian; Schreier, R.M.; Bleyer, Michael; Gelautz, Margrit

doi:10.1145/1497185.1497198

Cited by 10 publications

(4 citation statements)

References 7 publications

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“…Previous video codecs, in particular H.264/AVC, have been parallelized using mainly slice-level or macroblocklevel parallelism [17,21]. In H.264/AVC, as well as in HEVC, a picture can be partitioned in multiple arbitrarily sized slices for independent processing.…”

Section: Parallel Video Decoding With Hevcmentioning

confidence: 99%

Parallel HEVC Decoding on Multi- and Many-core Architectures

Ching

Alvarez-Mesa

Lucas

et al. 2012

J Sign Process Syst

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The Joint Collaborative Team on Video Decoding is developing a new standard named High Efficiency Video Coding (HEVC) that aims at reducing the bitrate of H.264/AVC by another 50%. In order to fulfill the computational demands of the new standard, in particular for high resolutions and at low power budgets, exploiting parallelism is no longer an option but a requirement. Therefore, HEVC includes several coding tools that allows to divide each picture into several partitions that can be processed in parallel, without degrading the quality nor the bitrate. In this paper we adapt one of these approaches, the Wavefront Parallel Processing (WPP) coding, and show how it can be implemented on multi-and many-core processors. Our approach, named Overlapped Wavefront (OWF), processes several partitions as well as several pictures in parallel. This has the advantage that the amount of (thread-level) parallelism stays constant during execution. In addition, performance and power results are provided for three platforms: a server Intel CPU with 8 cores, a laptop Intel CPU with 4 cores, and a TILE-Gx36 with 36 cores from Tilera. The results show that our parallel HEVC decoder is capable of achieving an

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Section: Parallel Video Decoding With Hevcmentioning

confidence: 99%

Parallel HEVC Decoding on Multi- and Many-core Architectures

Ching

Alvarez-Mesa

Lucas

et al. 2012

J Sign Process Syst

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“…Seitner et al [20] performed a simulation based comparison of several static MB-level parallelization approaches for resource-restricted environments. Baker et al [5] used Seitner's "single row" approach in their Cell implementation.…”

Section: Related Workmentioning

confidence: 99%

“…By exploiting the Cell memory hierarchy a scalability was achieved that approached the theoretical limit. In most of these works (e.g., [1,3,5,7,16,20,23]), the entropy decoding was not considered or mapped on a single core, which causes a scalability bottleneck.…”

Section: Related Workmentioning

confidence: 99%

A QHD-capable parallel H.264 decoder

Ching

Juurlink

2011

Proceedings of the International Conference on Supercomputing

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Video coding follows the trend of demanding higher performance every new generation, and therefore could utilize many-cores. A complete parallelization of H.264, which is the most advanced video coding standard, was found to be difficult due to the complexity of the standard. In this paper a parallel implementation of a complete H.264 decoder is presented. Our parallelization strategy exploits functionlevel as well as data-level parallelism. Function-level parallelism is used to pipeline the H.264 decoding stages. Datalevel parallelism is exploited within the two most time consuming stages, the entropy decoding stage and the macroblock decoding stage. The parallelization strategy has been implemented and optimized on three platforms with very different memory architectures, namely an 8-core SMP, a 64-core cc-NUMA, and an 18-core Cell platform. Evaluations have been performed using 4k×2k QHD sequences. On the SMP platform a maximum speedup of 4.5× is achieved. The SMP-implementation is reasonably performance portable as it achieves a speedup of 26.6× on the cc-NUMA system. However, to obtain the highest performance (speedup of 33.4× and throughput of 200 QHD frames per second), several cc-NUMA specific optimizations are necessary such as optimizing the page placement and statically assigning threads to cores. Finally, on the Cell platform a near ideal speedup of 16.5× is achieved by completely hiding the communication latency.

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“…By using a data-parallel decoding approach this part of the decoding process can be computed on multiple processing units. In this paper, we use a multicolumn approach for parallel macroblock processing [16]. Each frame is partitioned into vertical regions.…”

Section: ) Splitting 1-functional Partitioningmentioning

confidence: 99%

Development of a High-Level Simulation Approach and Its Application to Multicore Video Decoding

Seitner

Bleyer

Gelautz

et al. 2009

IEEE Trans. Circuits Syst. Video Technol.

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Abstract-In this paper, we introduce a high-level simulation methodology for the modeling of multicore video processing architectures. This method allows design space explorations of parallel video processing applications (VPAs). It is used to test the performance of running a VPA on arbitrary virtual hardware and software configurations. The method represents an alternative to performing a "complete" decoder implementation on a field-programmable gate array or an applicationspecific integrated circuit. The use of our method, therefore, yields the advantage of being considerably more time, labor, and cost efficient. As an application, we use our method for designing a parallel H.264 decoder targeting 720p25 resolution at bit-rates up to 50 Mb/s. Starting from a single-core decoder implementation, we use our simulator for estimating the performance gain when using a multicore architecture. We then detect the major performance bottlenecks in this multicore system and perform additional decoder splittings accordingly until we reach the targeted requirements. The use of functional splitting (i.e., pipelining) and data-parallel processing is demonstrated. The final H.264 decoder architecture is capable of fulfilling our performance requirements.Index Terms-Design exploration, H.264 decoder, parallel architectures, video processing.

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Evaluation of data-parallel splitting approaches for H.264 decoding

Cited by 10 publications

References 7 publications

Parallel HEVC Decoding on Multi- and Many-core Architectures

Parallel HEVC Decoding on Multi- and Many-core Architectures

A QHD-capable parallel H.264 decoder

Development of a High-Level Simulation Approach and Its Application to Multicore Video Decoding

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