Evaluation of design strategies for stochastically assembled nanoarray memories

Abstract

A key challenge facing nanotechnologies is learning to control uncertainty introduced by stochastic self-assembly. In this article, we explore architectural and manufacturing strategies to cope with this uncertainty when assembling nanoarrays, crossbars composed of two orthogonal sets of parallel nanowires (NWs) that are differentiated at their time of manufacture. NW deposition is a stochastic process and the NW encodings present in an array cannot be known in advance. We explore the reliable construction of memories from stochastically assembled arrays. This is accomplished by describing several families of NW encodings and developing strategies to map external binary addresses onto internal NW encodings using programmable circuitry. We explore a variety of different mapping strategies and develop probabilistic methods of analysis. This is the first article that makes clear the wide range of choices that are available.

Stochastic nanoscale addressing for logic

“…M [10]. During decoder assembly each NW codeword, c i , is modeled as a uniformly distributed independent random variable.…”

“…In either case, the NW decoder can be considered efficient if the number of MWs, M , is close to log 2 N A and N A is close to N . Both encoded NW decoders and RCDs have been shown to be efficient [10] [6] in that log 2 N A / < M < 3 log 2 N A / when N A is a large fraction of N . Now consider logic decoders that have N input NWs to a crossbar-based logic circuit.…”

“…For memory decoders, compound decoders have been shown to greatly reduce the required number of MWs. Memory decoders are far more efficient if g groups of N NWs are each connected to separate OCs [10], [6]. This is not the case for logic decoders.…”

“…We have analyzed the area occupied by memory decoders and crossbars for a variety of stochastic assembly methods to determine the conditions under which the area is minimized. We have studied encoded NW decoders [10], randomized-contact decoders [6], masked-based decoders [11], and decoders for radially encoded NWs [5]. In all cases tight bounds have been derived on M , the number of MWs required to address N a out of N NWs with high probability.…”

Voltage-controlled nano-addressing for nanosystem communication

“…Testing and feedback provide a one-to-one mapping between a nanoscale data line and an address. In such a case, precise control of the lengths of the lightly and heavily doped nanotube segments would be critical [5,7]. (4) In radial addressing, multi-walled carbon nanotubes are grown with lightly and heavily doped shells, wherein an etching process removes the heavily doped outer shells at precise locations, and defines the gate configurations at each crossing of nanoscale data lines and microscale address lines [22].…”