Evaluation of fermi level pinning in low, midgap and high workfunction metal cate electrodes on ALD and MOCVD HfO/sub 2/ under high temperature exposure

On the scaling issues and high-κ replacement of ultrathin gate dielectrics for nanoscale MOS transistors

“…<0.2 eV below the conduction band of polysilicon), which is a common figure used in the conventional process. This problem has received significant attentions recently and several methods have been proposed to solve it [183][184][185][186].…”

Mechanism of flatband voltage roll-off studied with Al2O3 film deposited on terraced oxide

“…1 13 For more accurate estimation of the charge terms, Brown et al 14 proposed Figure 2 shows the corresponding quadratic fitting of the data with Eq. The V FB -EOT data of all five terraced oxide samples are plotted together in Fig.…”

Future of silicon integrated circuit technology

“…Several achievements in finding new materials and developing new process for sub-100 nm device manufacturing have been made recently. These processes or materials include the elevated source/drain [9][10][11], plasma doping with flash or laser annealing [12][13][14], NiSi silicide [15][16], strained Si channel for mobility enhancement [17][18][19], silicon on insulator (SOI) [20][21][22], three-dimensional structure [23][24][25][26] high dielectric constant (high-k) gate insulator [28][29][30][31], metal gate [33][34], and low dielectric constant (low-k) interlayer insulator for interconnects [35][36]. These measures are already on schedule for future technology nodes [37].…”