Evaluation of GaN HEMT degradation by means of pulsed I–V, leakage and DLTS measurements

Abstract

The effects of short-term step-stress on the performance of GaN HEMTs have been evaluated for the first time by means of current deep-leveltransient-spectroscopy (DLTS) measurements. When subjected to high reverse gate bias the devices experienced an increase in the drain current dispersion as well as in the gate current. Current DLTS measurements carried out during the stress experiment show that the device degradation can be associated to the formation of a defect that is thermally activated with an energy of 0.5 eV.Introduction: While the outstanding RF performance of GaN-based high electron mobility transistors has been demonstrated by several authors [1, 2], their reliability still needs to be further improved. Decrease in output power and power added efficiency as a consequence of device knee-walkout and gate current degradation are amongst the most deleterious effects that can arise during device operation [3,4]. Zanoni et al. [5] have shown that high reverse biases can result in the formation of defects located at the edge of the gate contact. These defects have been related to the increase in both reverse currents as well as the device current-collapse. A similar degradation has been also related to defects that are thermally activated with an activation energy of 0.57 eV, as obtained by transient experiments carried out at different temperatures [6]. In this Letter, for the first time, we have studied the degradation of GaN HEMTs subjected to an electrical step-stress sequence by monitoring the formation of defects by means of current deep-level-transient-spectroscopy (DLTS) measurements. At each stress step, electrical parameters such as drain current dispersion, gate leakage and the DLTS signal associated with the defects that are forming during device degradation have been measured. As presented in the following, at the increasing of the reverse voltage applied to the gate Schottky junction we observed an increase in the DC gate leakage current level, an increase in the DLTS signal and larger drain current-collapse.

Correlation Between Epitaxial Layer Quality and Drain Current Stability of GaN/AlGaN/GaN Heterostructure Field-Effect Transistors

“…They are ranged between 0.3 and 0.5 eV. Trap levels at around this energy were widely observed by DLTS for GaN HFET structures [5], [13]- [17]. They are close to activation energy of 0.37 eV for a donor-like state related to N-vacancy in AlGaN that was confirmed by the X-ray photoelectron spectroscopy [35].…”

“…To study the trapping effects in GaN HFETs, various methods have been reported, including the capacitancevoltage measurement [8], the frequency-dependent conductance measurement [9]- [11], the low-frequency noise measurement [7], [9], and capacitance-mode [12] and current-mode [5], [13]- [17] deep-level transient spectroscopy (DLTS) measurements. Especially, the currentmode DLTS was widely used to analyze trapping effects in microwave devices [18], where gate capacitance is too small to be analyzed by capacitance-mode DLTS [19].…”

Study of deep traps in AlGaN/GaN high-electron mobility transistors by electrical characterization and simulation

“…However, a trap with E T = 0.5 eV has also been associated with GaN HEMT degradation during stress experiments. [21][22][23] Thus, trap E4 could also be linked to dry etching induced surface damage because defects formed during electron, proton, or ion irradiation are assumed to be jointly associated with nitrogen vacancies. 24 Trap E5 has an activation enthalpy E T = 0.64 eV and capture cross section σ T = 1.2 × 10 −14 cm 2 , and trap E6 has an activation enthalpy E T = 0.79 eV and capture cross section σ T = 5 × 10 −15 cm 2 .…”

Electrical and structural degradation of GaN high electron mobility transistors under high-power and high-temperature Direct Current stress

“…[1][2][3][4][5][6][7][8][9] Several mechanisms have been postulated to explain the various degradation patterns that have been observed. [8][9][10][11][12][13][14][15][16][17][18] Several studies [19][20][21][22][23][24][25] have shown the appearance of prominent physical damage (dimples, grooves, pits, trenches, and cracks) on the semiconductor surface under the edge of the gate after prolonged OFF-state stress. The damage extends through the GaN cap and the AlGaN barrier layer and in some extreme cases reaches into the GaN buffer layer.…”