Evaluation of high voltage cascode GaN HEMTs in parallel operation

Abstract

Paralleling devices is an effective way to achieve higher power applications while still having the convenience brought by discrete devices. However, very few papers investigate the challenges of paralleling Gallium Nitride high electron mobility transistors (GaN HEMTs) in cascode configuration, especially the potential failure modes and its related mechanisms. In this paper, a comprehensive study on paralleled high voltage cascode GaN HEMTs is presented. The influence of paralleling cascode GaN HEMTs on the circuit's stray inductance is studied. Potential operation failure modes and the mechanisms of the cascode GaN HEMTs parallel operation were analyzed in detail. The Ansoft Q3D FEA tool and SPICE-based simulation model were used together to quantify the impacts of the circuit and device mismatch on the paralleled GaN HEMTs operation. The SPICE model is validated by the experimental results

Vector control implementation in field programmable gate array for 200 kHz GaN‐based motor drive systems

“…Moreover, the package uses laminate surface mounted devices (SMD), which offers ultra‐low package inductance, and the top side cooling also provides the convenience of heat sink installation. Thus, the GaN system device (GS66516 T) is quite suitable for use in a high‐power density inverter [5, 6].…”